FUSB302MPX. datasheet(29/35 Pages) ONSEMI

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FUSB302

• Rev. 2

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Table 27. Interrupt

Address: 42h

Reset Value: 0x0000_0000

Type: Read/Clear

Bit #

Name

R/W/C

Size (Bits)

Description

I_VBUSOK

R/C

1: Interrupt occurs when VBUS transitions through 4.5 V. This

bit typically is used to recognize port partner during startup.

I_ACTIVITY

R/C

1: A change in the value of ACTIVITY of the CC bus has

occurred.

I_COMP_CHNG

R/C

1: A change in the value of COMP has occurred. Indicates

selected CC line has tripped a threshold programmed into the

MDAC.

I_CRC_CHK

R/C

1: The value of CRC_CHK newly valid. I.e. The validity of the

incoming packet has been checked.

I_ALERT

R/C

1: Alert software an error condition has occurred. An alert is

caused by:

TX_FULL: the transmit FIFO is full.

RX_FULL: the receive FIFO is full.

See Status1 bits.

I_WAKE

R/C

1: Voltage on CC indicated a device attempting to attach.

Software must then power up the clock and receiver blocks.

I_COLLISION

R/C

1: When a transmit was attempted, activity was detected on the

active CC line. Transmit is not done. The packet is received

normally.

I_BC_LVL

R/C

1: A change in host requested current level has occurred.

Table 28. FIFOs

Address: 43h

Reset Value: 0x0000_0000

Type: (see column below)

Bit #

Name

R/W/C

Size (Bits)

Description

7:0

TX/RX Token

Read or

Write

Writing to this register writes a byte into the transmit FIFO.

Reading from this register reads from the receive FIFO.

Each byte is a coded token. Or a token followed by a fixed

number of packed data byte (see token coding in Table 29).

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