AD9953_17 datasheet(17/32 Pages) AD

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Data Sheet

AD9953

Rev. B | Page 17 of 32

CFR1<9>: SDIO Input Only

CFR1<9> = 0 (default). The SDIO pin has bidirectional

operation (2-wire serial programming mode).

CFR1<9> = 1. The serial data I/O pin (SDIO) is configured as

an input only pin (3-wire serial programming mode).

CFR1<8>: LSB First

CFR1<8> = 0 (default). MSB first format is active.

CFR1<8> = 1. The serial interface accepts serial data in LSB

first format.

CFR1<7>: Digital Power-Down Bit

CFR1<7> = 0 (default). All digital functions and clocks are active.

CFR1<7> = 1. All non-IO digital functionality is suspended,

lowering the power significantly.

CFR1<6>: Not Used

CFR1<5>: DAC Power-Down Bit

CFR1<5> = 0 (default). The DAC is enabled for operation.

CFR1<5> = 1. The DAC is disabled and is in its lowest power

dissipation state.

CFR1<4>: Clock Input Power-Down Bit

CFR1<4> = 0 (default). The clock input circuitry is enabled for

operation.

CFR1<4> = 1. The clock input circuitry is disabled and the

device is in its lowest power dissipation state.

CFR1<3>: External Power-Down Mode

CFR1<3> = 0 (default). The external power-down mode

selected is the rapid recovery power-down mode. In this mode,

when the PWRDWNCTL input pin is high, the digital logic

and the DAC digital logic are powered down. The DAC bias

circuitry, PLL, oscillator, and clock input circuitry are not

powered down.

CFR1<3> = 1. The external power-down mode selected is the

full power-down mode. In this mode, when the PWRDWNCTL

input pin is high, all functions are powered down. This includes

the DAC and PLL, which take a significant amount of time to

power up.

CFR1<2>: Not Used

CFR1<1>: SYNC_CLK Disable Bit

CFR1<1> = 0 (default). The SYNC_CLK pin is active.

CFR1<1> = 1. The SYNC_CLK pin assumes a static Logic 0

state to keep noise generated by the digital circuitry at a

minimum. However, the synchronization circuitry remains

active (internally) to maintain normal device timing.

CFR1<0>: Not Used, Leave at 0

Control Function Register No. 2 (CFR2)

The CFR2 is used to control the various functions, features, and

modes of the AD9953, primarily related to the analog sections

of the chip.

CFR2<23:12>: Not Used

CFR2<11>: High Speed Sync Enable Bit

CFR2<11> = 0 (default). The high speed sync enhancement is off.

CFR2<11> = 1. The high speed sync enhancement is on. This

bit should be set when attempting to use the auto-

synchronization feature for SYNC_CLK inputs beyond 50 MHz,

(200 MSPS SYSCLK). See the Synchronizing Multiple AD9953s

section for details.

CFR2<10>: Hardware Manual Sync Enable Bit

CFR2<10> = 0 (default). The hardware manual sync function is off.

CFR2<10> = 1. The hardware manual sync function is enabled.

While this bit is set, a rising edge on the SYNC_IN pin will

cause the device to advance the SYNC_CLK rising edge by one

REFCLK cycle. Unlike the software manual sync enable bit, this

bit does not self clear. Once the hardware manual sync mode is

enabled, it will stay enabled until this bit is cleared. See the

Synchronizing Multiple AD9953s section for details.

CFR2<9>: CRYSTAL OUT Enable Bit

CFR2<9> = 0 (default). The CRYSTAL OUT pin is inactive.

CFR2<9> = 1. The CRYSTAL OUT pin is active. When active,

the crystal oscillator circuitry output drives the CRYSTAL OUT

pin, which can be connected to other devices to produce a

reference frequency. The oscillator will respond to crystals in

the range of 20 MHz to 30 MHz.

CFR2<8>: Not Used

CFR2<7:3>: Reference Clock Multiplier Control Bits

This 5-bit word controls the multiplier value out of the clock-

multiplier (PLL) block. Valid values are decimal 4 to 20 (0x04 to

0x14). Values entered outside this range will bypass the clock

multiplier. See the Phase-Locked Loop (PLL) section for details.

CFR2<2>: VCO Range Control Bit

This bit is used to control the range setting on the VCO.

When CFR2<2> == 0 (default), the VCO operates in a range of

100 MHz to 250 MHz. When CFR2<2> == 1, the VCO operates

in a range of 250 MHz to 400 MHz.

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