AD9953_17 datasheet(24/32 Pages) AD

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AD9953

Data Sheet

Rev. B | Page 24 of 32

External Shaped On-Off Keying Mode Operation

The external shaped on-off keying mode is enabled by writing

CFR1<25> to a Logic 1 and writing CFR1<24> to a Logic 0.

When configured for external shaped on-off keying, the

content of the ASFR becomes the scale factor for the data path.

The scale factors are synchronized to SYNC_CLK via the

I/O UPDATE functionality.

Synchronization; Register Updates (I/O UPDATE)

Functionality of the SYNC_CLK and I/O UPDATE

Data into the AD9953 is synchronous to the SYNC_CLK signal

(supplied externally to the user on the SYNC_CLK pin). The

I/O UPDATE pin is sampled on the rising edge of the

SYNC_CLK.

Internally, SYSCLK is fed to a divide-by-4 frequency divider to

produce the SYNC_CLK signal. The SYNC_CLK signal is

provided to the user on the SYNC_CLK pin. This enables

synchronization of external hardware with the device’s internal

clocks. This is accomplished by forcing any external hardware

to obtain its timing from SYNC_CLK. The I/O UPDATE signal

coupled with SYNC_CLK is used to transfer internal buffer

contents into the control registers of the device. The combina-

tion of the SYNC_CLK and I/O UPDATE pins provides the

user with constant latency relative to SYSCLK, and also ensures

phase continuity of the analog output signal when a new tuning

word or phase offset value is asserted. Figure 21 demonstrates

an I/O UPDATE timing cycle and synchronization.

Notes for synchronization logic:

1. The I/O UPDATE signal is edge detected to generate a

single rising edge clock signal that drives the register bank

flops. The I/O UPDATE signal has no constraints on duty

cycle. The minimum low time on I/O UPDATE is one

SYNC_CLK clock cycle.

2. The I/O UPDATE pin is set up and held around the rising

edge of SYNC_CLK and has zero hold time and 4 ns setup

time.

SYSCLK

SDI

SYNC_CLK

DISABLE

SCLK

TO CORE LOGIC

OSK

PROFILE<1:0>

I/O UPDATE

÷ 4

SYNC_CLK

GATING

EDGE

DETECTION

LOGIC

MEMORY

I/O BUFFER

LATCHES

Figure 21. I/O Synchronization Block Diagram

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