AD9953_17 datasheet(22/32 Pages) AD

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AD9953

Data Sheet

Rev. B | Page 22 of 32

PROGRAMMING AD9953 FEATURES

Phase Offset Control

A 14-bit phase offset (θ) may be added to the output of the phase

accumulator by means of the control registers. This feature

provides the user with two different methods of phase control.

The first method is a static phase adjustment where a fixed

phase offset is loaded into the appropriate phase offset register

and left unchanged. The result is that the output signal is offset

by a constant angle relative to the nominal signal. This allows

the user to phase align the DDS output with some external

signal, if necessary.

The second method of phase control is where the user regularly

updates the phase offset register via the I/O port. By properly

modifying the phase offset as a function of time, the user can

implement a phase modulated output signal. However, both the

speed of the I/O port and the frequency of SYSCLK limit the

rate at which phase modulation can be performed.

The AD9953 allows for a programmable continuous zeroing of

the phase accumulator as well as a clear and release or

automatic zeroing function. Each feature is individually

controlled via the CFR1 bits. CFR1<13> is the automatic clear

phase

accumulator bit. CFR1<10> clears the phase accumulator and

holds the value to zero.

Continuous Clear Bit

The continuous clear bit is simply a static control signal that,

when active high, holds the phase accumulator at zero for the

entire time the bit is active. When the bit goes low, inactive, the

phase accumulator is allowed to operate.

Clear and Release Function

When set, the auto-clear phase accumulator clears and releases

the phase accumulator upon receiving an I/O UPDATE. The

automatic clearing function is repeated for every subsequent

I/O UPDATE until the appropriate auto-clear control bit is

cleared.

Shaped On-Off Keying

The shaped on-off keying function of the AD9953 allows the

user to control the ramp-up and ramp-down time of an on-off

emission from the DAC. This function is used in burst

transmissions of digital data to reduce the adverse spectral

impact of short, abrupt bursts of data.

Auto and manual shaped on-off keying modes are supported.

The auto mode generates a linear scale factor at a rate

determined by the amplitude ramp rate (ARR) register

controlled by an external pin (OSK). Manual mode allows the

user to directly control the output amplitude by writing the

scale factor value into the amplitude scale factor (ASF) register.

The shaped on-off keying function may be bypassed (disabled)

by clearing the OSK enable bit (CFR1<25> = 0).

The modes are controlled by two bits located in the most signifi-

cant byte of the control function register (CFR). CFR1<25> is

the shaped on-off keying enable bit. When CFR1<25> is set, the

output scaling function is enabled and CFR1<25> bypasses the

function. CFR1<24> is the internal shaped on-off keying active

bit. When CFR1<24> is set, internal shaped on-off keying mode

is active; CFR1<24> is cleared, external shaped on-off keying

mode is active. CFR1<24> is a Don’t Care if the shaped on-off

keying enable bit (CFR1<25>) is cleared. The power-up

condition is shaped on-off keying disabled (CFR1<25> = 0).

Figure 20 shows the block diagram of the OSK circuitry.

AUTO Shaped On-Off Keying Mode Operation

The auto shaped on-off keying mode is active when CFR1<25>

and CFR1<24> are set. When auto shaped on-off keying mode

is enabled, a single scale factor is internally generated and

applied to the multiplier input for scaling the output of the DDS

core block (see Figure 20). The scale factor is the output of a

14-bit counter that increments/decrements at a rate determined

by the contents of the 8-bit output ramp rate register. The scale

factor increases if the OSK pin is high and decreases if the OSK

pin is low. The scale factor is an unsigned value such that all 0s

multiply the DDS core output by 0 (decimal) and 0x3FFF

multiplies the DDS core output by 16383 (decimal).

For those users who use the full amplitude (14 bits) but need

fast ramp rates, the internally generated scale factor step size

is controlled via the ASF<15:14> bits. Table 8 describes the

increment/decrement step size of the internally generated scale

factor per the ASF<15:14> bits.

A special feature of this mode is that the maximum output

amplitude allowed is limited by the contents of the amplitude

scale factor register. This allows the user to ramp to a value less

than full scale.

Table 8. Auto-Scale Factor Internal Step Size

ASF<15:14> (Binary)

Increment/Decrement Size

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