38

March 3, 2005

Ad vance

Inform ati o n

Erase and Programming Performance

Notes:

1. Typical program and erase times assume the following conditions: 25

typicals assume checkerboard pattern.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 5 on page 18 for further information on command definitions.

6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.

Latchup Characteristics

TSOP Pin and BGA Package Capacitance

Notes:

1. Sampled, not 100% tested.

Data Retention

Parameter

Typ (Note

1)

Max (Note 2)

Unit

Comments

Sector Erase Time

2

15

s

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

38

s

Byte Programming Time

10

300

µs

Excludes system level

overhead (Note 5)

Word Programming Time

12

360

µs

Chip Programming Time

(Note 3)

Byte Mode

5

40

s

Word Mode

3.5

30

s

Description

Min

Max

(including A9, OE#, and RESET#)

–1.0 V

11.0 V

–0.5 V

–100 mA

+100 mA

Parameter Symbol

Parameter Description

Test Setup

Typ

Max

Unit

Input Capacitance

TSOP

6

7.5

pF

Fine-pitch BGA

4.2

5.0

pF

Output Capacitance

TSOP

8.5

12

pF

Fine-pitch BGA

5.4

6.5

pF

Control Pin Capacitance

TSOP

7.5

9

pF

Fine-pitch BGA

3.9

4.7

pF

Parameter

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150°C10

Years

125°C20

Years