AM29SL400CB100REF datasheet(12/44 Pages) SPANSION

12 / 44 page

March 3, 2005

Ad vance

Inform ati o n

Writing Commands/Command Sequences

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to Word/Byte Configuration‚ on page 9

for more information.

The device features an Unlock Bypass mode to fa-

cilitate faster programming. Once the device enters

the Unlock Bypass mode, only two write cycles are

required to program a word or byte, instead of four.

The Word/Byte Program Command Sequence‚ on

page 15 has details on programming data to the de-

vice using both standard and Unlock Bypass com-

mand sequences.

An erase operation can erase one sector, multiple

sectors, or the entire device. Table 2 on page 11 and

Table 3 on page 11 indicate the address space that

each sector occupies. A sector address consists of

the address bits required to uniquely select a sector.

Command Definitions‚ on page 18 has details on

erasing a sector or the entire chip, or suspending/re-

suming the erase operation.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the in-

ternal register (which is separate from the memory

array) on DQ7–DQ0. Standard read cycle timings

apply in this mode. Refer to Autoselect Mode‚ on

page 11 and Autoselect Command Sequence‚ on

page 15 for more information.

ICC2 in the DC Characteristics table represents the

active current specification for the write mode. The

AC Characteristics‚ on page 28 contains timing

specification tables and timing diagrams for write op-

erations.

Program and Erase Operation Status

During an erase or program operation, the system

may check the status of the operation by reading the

status bits on DQ7–DQ0. Standard read cycle tim-

ings and ICC read specifications apply. Refer to Write

Operation Status‚ on page 18 for more information,

and to AC Characteristics‚ on page 28 for timing dia-

grams.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at VCC ± 0.2 V.

(Note that this is a more restricted voltage range

than VIH.) If CE# and RESET# are held at VIH, but

not within VCC ± 0.2 V, the device will be in the

standby mode, but the standby current will be

greater. The device requires standard access time

(tCE) for read access when the device is in either of

these standby modes, before it is ready to read data.

The device also enters the standby mode when the

RESET# pin is driven low. Refer to the next section,

RESET#: Hardware Reset Pin.

If the device is deselected during erasure or pro-

gramming, the device draws active current until the

operation is completed.

ICC3 in DC Characteristics‚ on page 24 represents

the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically en-

ables this mode when addresses remain stable for

tACC + 50 ns. The automatic sleep mode is indepen-

dent of the CE#, WE#, and OE# control signals.

Standard address access timings provide new data

when addresses are changed. While in sleep mode,

output data is latched and always available to the

system. ICC4 in the DC Characteristics table repre-

sents the automatic sleep mode current specifica-

tion.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the

RESET# pin is driven low for at least a period of tRP,

the device immediately terminates any operation

in progress, tristates all output pins, and ignores all

read/write commands for the duration of the RE-

SET# pulse. The device also resets the internal state

machine to reading array data. The operation that

was interrupted should be reinitiated once the device

is ready to accept another command sequence, to

ensure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS±0.2 V, the device

draws CMOS standby current (ICC4). If RESET# is

held at VIL but not within VSS±0.2 V, the standby

current is greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the

Flash memory, enabling the system to read the

boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a 0 (busy) until the

internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The

system can thus monitor RY/BY# to determine

whether the reset operation is complete. If RESET#

is asserted when a program or erase operation is not

executing (RY/BY# pin is 1), the reset operation is

completed within a time of tREADY (not during Em-

bedded Algorithms). The system can read data tRH

after the RESET# pin returns to VIH.

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