18

March 3, 2005

Ad vance

Inform ati o n

Command Definitions

Table 5. Am29SL400C Command Definitions

Legend:

X = Don’t care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17–A12 uniquely select any sector.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus

cycles are write operations.

4. Data bits DQ15–DQ8 are don’t cares for unlock and

command cycles.

5. Address bits A17–A11 are don’t cares for unlock and

command cycles, unless SA or PA required.

6. No unlock or command cycles required when reading

array data, unless SA or PA required.

7. The Reset command is required to return to reading array

data when device is in the autoselect mode, or if DQ5

goes high (while the device is providing status data).

8. The fourth cycle of the autoselect command sequence is

a read cycle.

9. The data is 00h for an unprotected sector and 01h for a

protected sector.

See “Autoselect Command

10. The Unlock Bypass command is required prior to the

Unlock Bypass Program command.

11. The Unlock Bypass Reset command is required to return

to reading array data when the device is in the unlock

bypass mode.

12. The system may read and program in non-erasing

sectors, or enter the autoselect mode, when in the Erase

Suspend mode. The Erase Suspend command is valid

only during a sector erase operation.

13. The Erase Resume command is valid only during the Erase

Suspend mode.

Write Operation Status

The device provides several bits to determine the sta-

tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,

and RY/BY#. Table 6 on page 22 and the following

Command

Sequence

(Note 1)

Bus Cycles (Notes 2-5)

First

Second

Third

Fourth

Fifth

Sixth

Addr

Dat

a

Addr

Dat

aAddr

Dat

aAddr Data Addr

Dat

aAddr

Dat

a

Read (Note 6)

1

RA

RD

Reset (Note 7)

1

XXX

F0

Manufacturer ID

Word

4

555

AA

2AA

55

555

90

X00

01

Byte

AAA

555

AAA

Device ID,

Top Boot Block

Word

4

555

AA

2AA

55

555

90

X01

70h

Byte

AAA

555

AAA

X02

70h

Device ID,

Bottom Boot Block

Word

4

555

AA

2AA

55

555

90

X01

FIh

Byte

AAA

555

AAA

X02

FIh

Sector Protect Verify

(Note 9)

Word

4

555

AA

2AA

55

555

90

(SA)

X02

XX00

XX01

Byte

AAA

555

AAA

(SA)

X04

00

01

Program

Word

4

555

AA

2AA

55

555

A0

PA

PD

Byte

AAA

555

AAA

Unlock Bypass

Word

3

555

AA

2AA

55

555

20

Byte

AAA

555

AAA

Unlock Bypass Program (Note 10) 2

XXX

A0

PA

PD

Unlock Bypass Reset (Note 11)

2

XXX

90

XXX

00

Chip Erase

Word

6

555

AA

2AA

55

555

80

555

AA

2AA

55

555

10

Byte

AAA

555

AAA

AAA

555

AAA

Sector Erase

Word

6

555

AA

2AA

55

555

80

555

AA

2AA

55

SA

30

Byte

AAA

555

AAA

AAA

555

Erase Suspend (Note 12)

1

XXX

B0

Erase Resume (Note 13)

1

XXX

30