TUSB5052 datasheet(41/84 Pages) TI

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6–1

6 DMA Controller

Table 6–1 outlines the five DMA channels and their associated transfer directions. Four channels are provided for

data transfer between the host and the UARTs. DMA-5 is provided for half-duplex parallel-port transfer (the transfer

direction is defined by the DIR bit in the PPMCR register).

Table 6–1. DMA Channel Allocation

DMA

CHANNEL

TRANSFER

DIRECTION

COMMENTS

DMA-1

Host to UART-1

DMA writes to UART-1 TDR register

DMA-2

Host to UART-2

DMA writes to UART-2 TDR register

DMA-3

UART-1 to host

DMA reads from UART-1 RDR register

DMA-4

UART-2 to host

DMA reads from UART-2 RDR register

DMA-5

Host to/from P-port

DMA reads/writes from/to PPDAT register. Direction is defined by DIR-bit in PPMCR register.

6.1

DMA Controller Registers

Each DMA channel can point to one of seven EDBs (EDB[7:1]) and transfer data to/from a UART channel or the

parallel port. The DMA can move data from a given out-point buffer (defined by EDB) to the destination port. Similarly,

the DMA can move data from a port to a given input-endpoint buffer. Two modes of DMA transfers are supported:

burst and continuous.

In burst (CNT = 0) mode the DMA stops at the end of a block-data transfer (or if an error condition occurred) and

interrupts the MCU. It is the responsibility of the MCU to update the X/Y bit and the NAK bit in the EDB.

In continuous (CNT = 1) mode, at the end of a block transfer the DMA updates the byte-count and NAK-bit in the EDB

when receiving. In addition, it uses the X/Y-bit to switch automatically, without interrupting the MCU (the X/Y bit toggle

is performed by the UBM). The DMA stops only when a timeout or error condition occurs. When the DMA is

transmitting (from the X/Y buffer) it continues alternating between X/Y buffers until it detects a byte-count smaller than

the buffer size (buffer size is typically 64 bytes). At that point it completes the transfer, then stops.

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