TUSB5052 datasheet(45/84 Pages) TI

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6–5

6.1.4

DMACSR[4–3]: DMA Control and Status Register (2 UART-Receive Channels)

This register is used to define the transaction-timeout value. In addition, this register contains a completion code that

reports any errors or a time-out condition.

TEN

TXFT

OVRUN

R/W

R/C

BIT

NAME

RESET

FUNCTION

OVRUN

Overrun condition bit. This bit is set by DMA and cleared by the MCU (see Table 6–3).

OVRUN = 0

No overrun condition

OVRUN = 1

Overrun condition detected. When IEN = 0, this bit does not clear the EN bit in DMACDR; therefore,

the DMAC stays enabled, ready for the next transaction. Clears when the MCU writes a 1. Writing

a 0 has no effect.

TXFT

Transfer timeout condition bit (see Table 6–3)

TXFT = 0

DMA stopped transfer without time-out

TXFT = 1

DMA stopped due to transaction time-out. When IEN = 0, this bit does not clear the EN bit in

DMACDR; therefore, the DMAC stays enabled, ready for the next transaction. Clears when the

MCU writes a 1. Writing a 0 has no effect.

6-2

C[4:0]

This field is used to define the transaction time-out value in 1 ms increments. This value is loaded to a down

counter every time a byte transfer occurs. The down counter is decremented every SOF pulse (1 ms). If the

counter decrements to zero, it sets TXFT =1 (in DMACSR register) and halts the DMA transfer. The counter starts

counting only when TEN = 1 and EN = 1 (in DMACDR)

and the first byte has been received. See Figure 6–1).

00000 = 0ms time-out

11111 = 31 ms time-out

TEN

Transaction timeout counter enable/disable bit

TEN = 0 Counter is disabled (does

not time out).

TEN = 1 Counter is enabled.

Table 6–3. DMA IN-Termination Condition

IN-Termination

TXFT

OVRUN

Comments

UART error

UART eror condition detected

UART partial-packet

This condition occurs when UART receiver has no more data for host (data starvation).

UART time-out

This condition occurs when X and Y input-buffers are full and the UART FIFO is full (host is busy).

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