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AD9858 数据表(PDF) 4 Page - Analog Devices

部件名 AD9858
功能描述  1 GSPS Direct Digital Synthesizer
PDF  32 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9858 数据表(HTML) 4 Page - Analog Devices

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AD9858
Rev. A | Page 4 of 32
Parameter
Temp
Test
Level
Min
Typ
Max
Unit
OUTPUT PHASE NOISE CHARACTERISTICS (@ 100 MHz IOUT
with 700 MHz REFCLK)
@ 100 Hz Offset
Full
V
–125
dBc/Hz
@ 1 kHz Offset
Full
V
–140
dBc/Hz
@ 10 kHz Offset
Full
V
–148
dBc/Hz
@ 100 kHz Offset
Full
V
–150
dBc/Hz
@ 1 MHz Offset
Full
V
–150
dBc/Hz
@ 10 MHz Offset
Full
V
–150
dBc/Hz
PHASE DETECTOR AND CHARGE PUMP
Phase Detector Frequency
Full
VI
150
MHz
Phase Detector Frequency (Divide-by-4 Enabled)4
Full
VI
400
MHz
Charge Pump Sink and Source Current5
Full
VI
4
mA
Fast Lock Current (Acquisition Only)
Full
VI
7
mA
Open-Loop Current (Acquisition Only)
Full
VI
30
mA
Sink and Source Current Absolute Accuracy6
Full
V
2.5
%
Sink and Source Current Matching6
Full
V
1
%
Input Sensitivity PDIN and DIVIN (50 Ω)7
Full
IV
–15
0
dBm
Input Impedence PDIN and DIVIN (Single-Ended)
Full
V
1
kΩ
Phase Noise @ 100 MHz Input Frequency
@ 10 kHz Offset
Full
V
110
dBc/Hz
@ 100 kHz Offset
Full
V
140
dBc/Hz
@ 1 MHz Offset
Full
V
148
dBc/Hz
Charge Pump Output Range8
Full
V
CPVDD
V
MIXER
IFOUT9
Full
V
400
MHz
FRF
Full
VI
2
GHz
FLO
Full
VI
2
GHz
Conversion Gain
Full
VI
0.0
3.5
dB
LO Level
Full
VI
–10
+5
dBm
RF Level
Full
VI
–20
dBm
Input IP3
Full
VI
5
9
dBm
1 dB Input Compression Power10
Full
VI
–3
dBm
Input Impedance (Single-Ended)
LO
Full
V
1
kΩ
RF
Full
V
1
kΩ
LOGIC INPUTS
Logic 1 Voltage
Full
VI
2.0
V
Logic 0 Voltage
Full
VI
0.8
V
Logic 1 Current
Full
VI
12
µA
Logic 0 Current
Full
VI
12
µA
Input Capacitance
Full
V
3
pF
POWER SUPPLY
PDISS (Worst-Case Conditions—Everything on
PFD Input Frequency 150 MHz)
Full
VI
2
2.5
W
PDISS (DAC and DDS Core Only Worst-Case)
Full
VI
1.7
2
W
PDISS (Power-Down Mode)
Full
VI
65
100
mW
PDISS Mixer Only
Full
VI
60
75
mW
PDISS PFD and CP (@ 100 MHz) Only
Full
VI
350
435
mW



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