AD9858 datasheet(19/32 Pages) AD

19 / 32 page

AD9858

Rev. A | Page 19 of 32

40ns

80ns

TIME

120ns

160ns

DELTA FREQUENCY RAMP RATE WORD (

≥8ns)

8ns

16ns

TIME

24ns

32ns

DELTA FREQUENCY TUNING WORD

Figure 32. Frequency vs. Time Plots for a Given Sweep Profile

The delta frequency ramp rate word (DFRRW) functions as a

countdown timer, in which the value of the DFRRW is decre-

mented at the rate of SYSCLK/8. This means that the most rapid

frequency word update occurs when a value of 1 is loaded into

the DFRRW, and results in a frequency increment at 1/8 of the

SYSCLK rate. With a SYSCLK of 1 GHz, the frequency can be

incremented at a maximum rate of 125 MHz (DFRRW = 1).

The delta frequency tuning word (DFTW) must specify

whether the frequency sweep should proceed up or down from

the starting frequency (FTW). Therefore, the DFTW is

expressed as a twos complement binary value, in which positive

indicates up and negative indicates down.

A DFRRW value of 0 written to the register stops all frequency

sweeping. There is no automatic stop-at-a-given-frequency

function. The user must calculate the time interval required to

reach the final frequency and then issue a command to write 0

into the DFRRW register. The time required for a frequency

sweep is calculated by the following formula

DFTW

DFRRW

SYSCLK

−

where:

T is the duration of the sweep in seconds.

fS is the starting frequency determined by

SYSCLK

FTW

fF is the final frequency.

The delta frequency step size is given by

SYSCLK

DFTW

∆

remembering that DFTW is a signed (twos complement) value.

The time between each frequency step (∆t) is given by

SYSCLK

DFRRW

∆

The value of the stop frequency fF is determined by

∆

Returning to Starting Frequency

The original frequency tuning word (FTW), which was written

into the frequency tuning register, does not change at any time

during a sweeping operation. This means that the DDS may be

returned to the sweep starting frequency at any time during a

sweep. Setting the control bit named autoclear frequency

accumulator forces the frequency accumulator to zero, instantly

returning the DDS to the frequency stored as FTW.

Full-Sleep Mode

Setting all of the power-down bits in the control function

condition, the clocks associated with the various functional

blocks of the device are turned off, thereby offering a significant

power savings.

SYNCHRONIZATION

SYNCLK and FUD Pins

Timing for the AD9858 is provided via the user-supplied

REFCLK input. The REFCLK input is buffered and is the source

for the internally generated SYSCLK. The frequency of SYSCLK

can be either the same as REFCLK or half that of REFCLK (via

a programmable divide-by-2 function set in the control

function register CFR). The REFCLK input is capable of

handling input frequencies as high as 2 GHz. However, the

device is designed for a maximum SYSCLK frequency of 1 GHz.

Thus, it is mandatory that the divide-by-2 SYSCLK function be

enabled when the frequency of REFCLK is greater than 1 GHz.

AD9858 数据表(PDF) 19 Page - Analog Devices

AD9858 数据表(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表下载

链接网址

AD9858 数据表(PDF) 19 Page - Analog Devices

AD9858 数据表(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表 下载

链接网址

数据表下载