AD9858

Rev. A | Page 20 of 32

SYSCLK serves as the sample clock for the DAC and is fed to a

divide-by-8 frequency divider to produce SYNCLK. SYNCLK is

provided to the user on the SYNCLK pin. This enables

synchronization of external hardware with the AD9858’s

internal DDS clock. External hardware that is synchronized to

the SYNCLK signal can then be used to provide the frequency

update (FUD) signal to the AD9858. The FUD signal and

SYNCLK are used to transfer the internal buffer register

contents into the memory registers of the device. Figure 33

shows a block diagram of the synchronization methodology,

and Figure 34 shows an I/O synchronization timing diagram.

Note that SYNCLK is also used to synchronize the assertion of

the profile select pins (PS0, PS1). The FUD, PS0, and PS1 pins

must be set up and held around the rising edge of SYNCLK.

These device inputs are designed for zero hold time and 3.5 ns

setup time.

REGISTER

MEMORY

EDGE

DETECTION

LOGIC

REFCLK

P0, P1

FUD

SYNCLK

0

2 GHz DIVIDER

DISABLE

SYNCLK

DISABLE

TO CORE LOGIC

BUFFER

MEMORY

÷ 2

D

Q

WR

ADDR

DATA

SYNCLK

D

Q

÷ 8

Figure 33. I/O Synchronization Block Diagram

SYNCLK

SYSCLK

FUD REGISTERED

FUD EDGE DETECTED

FUD REGISTERED

FUD EDGE DETECTED

VALUE 2

VALUE 1

IO BUFFER

MEMORY

CONTROL

REGISTER

DATA

VALUE 0

VALUE 1

VALUE 2

(ASYNCHRONOUSLY LOADED VIA I/O PORT)

FUD

*

THE RISING EDGE OF SYNCLK DURING THE HIGH STATE OF THE UPDATEREGS SIGNAL CAUSES THE BUFFER MEMORY CONTENTS TO BE

TRANSFERRED INTO THE CONTROL REGISTERS. SIMILARLY, A STATE CHANGE ON THE PS0 OR PS1 PINS IS EQUIVALENT TO ASSERTING A VALID

FUD SEQUENCE. NOTE: I/O UPDATES ARE SYNCHRONOUS TO THE SYNCLK SIGNAL, REGARDLESS OF THE SYNCHRONIZATION MODE SELECTED.

(ASYNCHRONOUSLY LOADED VIA I/O PORT)

Figure 34. I/O Synchronization Timing Diagram