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AD9858

Rev. A | Page 16 of 32

Phase-Frequency Detector

The phase detector has two inputs, PDIN and DIVIN. Both are

analog inputs that can be operated in differential or single-

ended mode. Both are designed to operate at frequencies up to

150 MHz, although signals of up to 400 MHz can be

accommodated on the inputs when the divide-by-4 functions

are used. The expected input level for both the PD and DIV

inputs is in the range of 800 mV p-p (differential), 400 mV p-p

(single-ended). A programmable divider that offers division

ratios of M, N = {1, 2, 4} immediately follows the input. The

division ratio is controlled by means of the control

function register.

Charge Pump

The charge pump output reference current is determined by an

external resistor (~2.4 kΩ), which establishes a 500 µA

maximum internal baseline current (ICP0). The baseline current

is scaled to provide the appropriate drive current for the CP’s

various operating modes (frequency detect mode, wide closed-

loop, and final closed-loop). The amount of scaling in each

mode is programmable by means of the values stored in the

control function register, giving the user maximum flexibility of

the PLL’s frequency locking capability.

The CP polarity can be configured as either positive or negative

with respect to the PD input. When the CP polarity is positive, if

the DIV input leads the PD input, the charge pump attempts to

decrease the voltage at the VCO control node. If the DIV input

lags the PD input, the charge pump works to increase the

voltage at the VCO control node. When the CP polarity is

negative, the opposite occurs. This allows the user to define

either input as the feedback path. This also allows the AD9858

to accommodate ground-referenced or supply-referenced

VCOs. This functionality is defined by the charge pump polarity

(CPP) bit in the control function register. When CPP = 0

(default), the charge pump is set up for operation with a

ground-referenced VCO. When CPP = 1, the charge pump is set

up for a supply-referenced VCO.

Internal to the CP, the ICP0 current is scaled to provide different

output drive current values for the various modes of operation.

In its normal operating mode, the final closed-loop mode can

be programmed to scale ICP0 by 1, 2, 3, or 4. Setting the charge

pump current offset bit, CFR<13>, applies a 2 mA offset to the

programmed charge pump current, allowing scaler values of ICP0

of 5, 6, 7, or 8. The wide closed-loop mode can be programmed

to scale ICP0 by 0, 2, 4, 6, 8, 10, 12, or 14. The frequency detect

mode can be programmed to scale ICP0 by 0, 20, 40, or 60. The

different modes of operation, controlled by the fast-locking

logic, are discussed in the next section

The CP has an independent set of power pins that can operate

at up to 5.25 V. While the device can operate from ground to

rail, the voltage compliance should be kept in the range of 0.5 V

to 4.5 V to ensure the best steady-state performance. The

combination of programmable output current, programmable

polarity, wide compliance range, and proprietary fast-lock

capability offers the flexibility necessary for the digital PLL to

operate within a broad range of PLL applications.

Fast-Locking Logic

The charge pump includes a fast-locking algorithm that helps to

overcome the traditional limitations of PLLs with regard to

frequency switching time. The fast-locking algorithm works in

conjunction with the loop filter shown in Figure 29 to provide

extremely fast frequency switching performance.

Based on the error seen between the feedback signal and the

reference signal, the fast-locking algorithm puts the charge

pump into one of three states: frequency detect mode, a wide

closed-loop mode, and a final closed-loop mode. In the

frequency detect mode, the feedback and reference signals are

registering substantial phase and frequency errors. Rather than

operating in a continuous closed-loop feedback mode, the

charge pump supplies a fixed current of the correct polarity to

the VCO control node that drives the loop towards frequency

lock. Once frequency lock is detected, the fast-locking logic

shifts the part into one of the closed-loop modes. In the closed-

loop modes, either wide or final, the charge pump supplies

current to the loop filter as directed by the phase-frequency

detector PFD. The frequency-detect mode is intended to bring

the system to a level of frequency lock from which the

intermediary closed-loop system can quickly achieve phase lock.

The level of frequency lock accuracy aimed for is typically

referred to as the lock range. Once the frequency is within the

lock range, the time required to achieve phase lock can be

determined by standard PLL transient analysis methods. Note

that the charge pump current sources associated with the

frequency detect mode are connected to Pin 64, while the closed

loop current sources are connected to Pins 65 and 66. Pin 64 is

connected directly to the loop filter zero compensation

capacitor, as shown in Figure 29. This connection allows the

smoothest transition from the frequency detect mode to the

closed-loop modes and enables faster overall switching times.

Pins 65 and 66 are connected to the loop filter in the

conventional manner.

CPFL

AD9858

Figure 29. Symbolic Representation of

Charge Pump to Loop Filter Connection

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