AD9858

Rev. A | Page 9 of 32

Pin No.

Mnemonic

I/O

Description

71

DIV

I

Phase Frequency Detector Feedback Input.

72

DIV

I

Phase Frequency Detector Feedback Complementary Input. Note that when the DIV port is

operated in single-ended mode, DIV should be decoupled to AVDD with a 0.1 µF capacitor.

78

DACBP

DAC Baseline Decoupling Pin, Typically Bypassed to Pin 77 with a 0.1 µF Capacitor.

79

DACISET

I

A Resistor Connected from DACISET to AGND Establishes the Reference Current for the DAC.

81, 82

IOUT

O

DAC Output.

83, 84

IOUT

O

DAC Complementary Output.

91

SPSELECT

I

I/O Port Serial/Parallel Programming Mode Select Pin. Logic 0: serial programming mode.

Logic 1: parallel programming mode.

92

RESET

I

Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9858 to its default

operating conditions.

97, 98

PS0, PS1

I

Used to Select One of the Four Internal Profiles. These pins are synchronous to the

SYNCLK output.

99

FUD

I

Frequency Update. The rising edge transfers the contents of the internal buffer registers to the

memory registers. This pin is synchronous to the SYNCLK output.

100

SYNCLK

O

Clock Output Pin that Serves as a Synchronizer for External Hardware. SYNCLK runs at REFCLK/8.