10
10
COM20051 MEMORY MAPPING
The COM20051 maps the Arcnet core into a
256 byte page of data memory space. This
memory is physically located internally to the
device and itrquote s default base address on
power up is 0000h. This 256 byte page can be
logically
located
anywhere
within
the
64K
external data memory space while physically
remaining on board. The location of this 256 byte
page is pointed to by the Address Decode
Register in the device. This Address Decode
Register holds the upper 8 bits of the 16 bit
address at which the 256 byte page boundary
will start. The address of this Address Decode
Register is FFFFh. This register is also logically
located in external data memory space but
physically located on the device. This register
must be written to on power-up to properly locate
the Arcnet core. .
The user must ensure that the Arcnet corerquote
s 256 byte page does not conflict with external
memory, otherwise data
bus contention will
result. As an example, if the user has 32K of
external data memory located from 0000h to
7FFFh then the Arcnet core should be mapped
above this area, 8000H is suggested. The user
will write 80h to address FFFFh on power up to
properly map the core to this location.
ARCNET
Network
Core
-
Overview
and
Architecture
ARCNET is a baseband token passing network
protocol
(ANSI
878.1).
ARCNET
features
deterministic behavior, hardware-based network
configuration, flexible topologies, several data
rates, and multiple media support.
Data rates
varying from 5 Mbps to 156 Kbps and message
sizes from 1 to 508 bytes are supported.
Supported media includes RS-485, twisted pair,
coax, fiber optic, and powerline in bus, star or
tree
topologies.
ARCNET
has
enjoyed
widespread use in the industrial community,
finding a home in such applications as I/O
control/acquisition,
multi-processor
communications,
point-of-sale
terminals,
in-
vehicle navigation systems, data acquisition
systems, remote sensing,
avionics,
machine
control,
embedded
computing,
building
automation, robotics, consumer products, and
security systems.
The ARCNET core used in the COM20051 is
similar in architecture to SMSC's 200XX series of
Industrial ARCNET Controllers.
The ARCNET
core of the COM20051 contains a 1K x 8 internal
RAM
for
packet
buffering,
Duplicate
ID
Detection, Receive All Mode, New Next ID
Indicator,
Excessive
NACK
Interrupt,
Programmable Data Rates, Backplane Mode,
Programmable
Transmitter
Enable,
Polarity
Receive Activity, Reconfiguration, Token Seen
Indicators, and Network Mapping hooks.
The
ARCNET
core
of
the
COM20051
uses
a
software-programmable node ID, enabling the
user to program the Node ID according to the
application needs. The Node ID can be stored in
an electronic medium or changed with the
switch.
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