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COM20051 数据表(PDF) 36 Page - List of Unclassifed Manufacturers

部件名 COM20051
功能描述  Integrated Microcontroller and ARCNET (ANSI 878.1) Interface
PDF  82 Pages
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制造商  ETC1 [List of Unclassifed Manufacturers]
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标志 ETC1 - List of Unclassifed Manufacturers

COM20051 数据表(HTML) 36 Page - List of Unclassifed Manufacturers

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Table 13 - Setup Register
BIT
BIT NAME
SYMBOL
DESCRIPTION
7
Pulse1 Mode
P1MODE
This bit determines the type of PULSE1 output driver used in
Backplane Mode. When high, a push/pull output is used.
When low, an open drain output is used. The default is open
drain.
6
Four NACKS
FOUR NACKS
This bit, when set, will cause the EXNACK bit in the Diagnostic
Status Register to set after four NACKs to Free Buffer Enquiry
are detected by the ARCNET core. This bit, when reset, will set
the EXNACK bit after 128 NACKs to Free Buffer Enquiry. The
default is 128.
5
ET3
ET3
This bit, when set, scales down protocol timeout values of
Response Time and Idle Time but not Reconfiguration Time to
optimize network performance in short topologies. Provides a
scaling factor of ÷ 3. Defaults to a zero. Must be reset to be
ARCNET compliant.
4
Receive All
RCVALL
This bit, when set, allows the COM20051 to receive all valid
data packets on the network, regardless of their destination ID.
This mode can be used to implement a network monitor with the
transmitter on- or off-line. Note that ACKs are only sent for
packets received with a destination ID equal to the
COM20051's programmed node ID. This feature can be used
to put the COM20051 in a 'listen-only' mode, where the
transmitter is disabled and the COM20051 is not passing
tokens. Defaults low.
3,2,1
Clock
Prescaler Bits
3,2,1
CKP2,1,0
These bits are used to determine the data rate of the
COM20051. The following table is for a 40MHz crystal:
Response
CKP3 CKP2 CKP1
DIVISOR
CLOCK
0
0
0
8
2.5 Mbps
0
0
1
16
1.25 Mbps
0
1
0
32
625 Kbps
0
1
1
64
312.5 Kbps
1
0
0
128
156.25 Kbps
1
0
1
256
Reserved
1
1
0
Reserved
1
1
1
Reserved
NOTE: The lowest data rate achievable by the COM20051 is
156.25 Kbps. A divide by 256 is provided for those systems
that use faster clock speeds. Defaults to 000 or 2.5 Mbps.
0
Slow
Arbitration
Select
SLW-ARB
This bit, when set, will divide the arbitration clock by 2. Memory
cycle times will increase when slow arbitration is selected.
NOTE: For 5 Mbps operation, SLOWARB must be set.
Defaults to low.



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