COM20051 datasheet(34/82 Pages) ETC1

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Table 12 - Configuration Register

BIT

BIT NAME

SYMBOL

DESCRIPTION

Reset

RESET

A software reset of the ARCNET core is executed by

writing a logic "1" to this bit. A software reset does not

reset the microcontroller interface mode, nor does it

affect the Configuration Register. The only registers that

the software reset affect are the Status Register, the

Next ID Register, and the Diagnostic Status Register.

This bit must be brought back to logic "0" to release the

reset. The Software Reset applies only to the ARCNET

core. It does not apply to the 8051 microcontroller of the

COM20051.

Command

Chaining

Enable

CCHEN

This bit, if high, enables the Command Chaining

operation of the device. Please refer to the Command

Chaining section for further details. A low level on this

bit ensures software compatibility with previous SMSC

ARCNET devices.

Transmit

Enable

TXEN

When low, this bit disables transmissions by keeping

nPULSE1, nPULSE2 if in non-Backplane Mode, and

nTXENABLE inactive. When high, it enables the above

signals to be activated during transmissions. This bit

defaults low upon reset. This bit is typically enabled

once the Node ID is determined, and never disabled

during normal operation. Please refer to the Improved

Diagnostics section for details on evaluating network

activity.

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