39
39
• The pointer may now be read to determine
how many transfers were completed.
The
software
flow
for
controlling
the
Configuration, Node ID, Tentative ID, and Next
ID
registers
is
generally
limited
to
the
initialization sequence and the maintenance of
the network map.
Additionally, it is necessary to understand the
details of how the other Internal Registers are
used in the transmit and receive sequences and
to know how the internal RAM buffer is properly
set up. The sequence of events that tie these
actions together is discussed as follows.
Selecting RAM Page Size
During normal operation, the 1K x 8 of RAM is
divided into two pages of 512 bytes each. The
page to be used is specified in the "Enable
Transmit
(Receive)
from
(to)
Page
fnn"
command, where "nn" specifies page 0 or 1.
This allows the user to have constant control
over the allocation of RAM.
When the Offset bit "f" (bit 5 of the "Enable
Transmit
(Receive)
from
(to)
Page
fnn"
command word) is set to logic "1", an offset of
256 bytes is added to the page specified. For
example: to transmit from the second half of
page 0, the command "Enable Transmit from
Page fnn" (fnn=100 in this case) is issued by
writing 0010 0011 to the Command Register.
This allows a finer resolution of the buffer pages
without affecting software compatibility.
This
scheme
is
useful
for
applications
which
frequently use packet sizes of 256 bytes or less,
especially
for
microcontroller
systems
with
limited memory capacity. The remaining portions
of the buffer pages which are not allocated for
current transmit or receive packets may be used
as temporary storage for previous network data,
packets to be sent later, or as extra memory for
the system, which may be indirectly accessed.
If the device is configured to handle both long
and short packets (see "Define Configuration"
command), then the receive page should always
be 512 bytes long because the user never knows
what the length of the receive packet will be. In
this case, the transmit page may be made 256
bytes long, leaving at least 256 bytes free at any
given
time.
Please
note
that
it
is
the
responsibility of software to reserve 512 bytes for
the receive page if the device is configured to
handle long packets. The ARCNET core does
not check page boundaries during reception.
If the device is configured to handle only short
packets, then both transmit and receive pages
may be allocated as 256 bytes long, allowing two
receive and two transmit packets.
The general rule which may be applied to
determine where in RAM a page begins is as
follows:
Address = (nn x 512) + (f x 256).
Transmit Sequence
During a transmit sequence, the microcontroller
selects a 256 or 512 byte segment of the RAM
buffer and writes into it. The appropriate buffer
size is specified in the "Define Configuration"
command. When long packets are enabled, the
ARCNET core interprets the packet as either a
long or short packet, depending on whether the
buffer address 2 contains a zero or non-zero
value.
The format of the buffer is shown in
Figure 11.
Address 0 contains the Source
Identifier
(SID);
Address
1
contains
the
Destination Identifier (DID); Address 2 (COUNT)
contains, for short packets, the value 256-N,
where N represents the number of information
bytes in the message, or for long packets, the
value 0, indicating that it is indeed a long packet.
In the latter case, Address 3 (COUNT) would
contain the value 512-N, where N represents the
number of information bytes in the message.
The
SID
in
Address
0
is
used
by
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