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PIC18LF4520E/SPQTP 数据表(PDF) 154 Page - Microchip Technology

部件名 PIC18LF4520E/SPQTP
功能描述  28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PDF  390 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

PIC18LF4520E/SPQTP 数据表(HTML) 154 Page - Microchip Technology

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PIC18F2420/2520/4420/4520
DS39631A-page 152
Preliminary
 2004 Microchip Technology Inc.
16.4.4
HALF-BRIDGE MODE
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output signal
is output on the P1A pin, while the complementary PWM
output signal is output on the P1B pin (Figure 16-4). This
mode can be used for half-bridge applications, as shown
in Figure 16-5, or for full-bridge applications where four
power switches are being modulated with two PWM
signals.
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits,
PDC6:PDC0, sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 16.4.6
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTD<5> data latches, the
TRISC<2> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 16-4:
HALF-BRIDGE PWM
OUTPUT
FIGURE 16-5:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
Period
Duty Cycle
td
td
(1)
P1A(2)
P1B(2)
td = Dead-Band Delay
Period
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
PIC18F4X2X
P1A
P1B
FET
Driver
FET
Driver
V+
V-
Load
+
V
-
+
V
-
FET
Driver
FET
Driver
V+
V-
Load
FET
Driver
FET
Driver
PIC18F4X2X
P1A
P1B
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit



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