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V62/13624-01XE-R 数据表(PDF) 36 Page - Texas Instruments |
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V62/13624-01XE-R 数据表(HTML) 36 Page - Texas Instruments |
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36 / 77 page  SDA SCL 1/fSCL tHD,DAT tSU,DAT tHD,STA tSU,STA tHD,STA tSU,STO tSP 36 MSP430F2132-EP SLAS913A – JULY 2013 – REVISED AUGUST 2013 www.ti.com Product Folder Links: MSP430F2132-EP Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated 5.28 USCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 8) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fUSCI USCI input clock frequency Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ± 10% fSYSTEM MHz fSCL SCL clock frequency 2.2 V, 3 V 0 400 kHz tHD,STA Hold time (repeated) START fSCL ≤ 100 kHz 2.2 V, 3 V 4 µs fSCL > 100 kHz 0.6 tSU,STA Setup time for a repeated START fSCL ≤ 100 kHz 2.2 V, 3 V 4.7 µs fSCL > 100 kHz 0.6 tHD,DAT Data hold time 2.2 V, 3 V 0 ns tSU,DAT Data setup time 2.2 V, 3 V 250 ns tSU,STO Setup time for STOP 2.2 V, 3 V 4 µs tSP Pulse duration of spikes suppressed by input filter 2.2 V 45 150 605 ns 3 V 45 100 605 Figure 8. I2C Mode Timing |
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