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V62/13624-01XE-R 数据表(PDF) 56 Page - Texas Instruments |
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V62/13624-01XE-R 数据表(HTML) 56 Page - Texas Instruments |
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56 / 77 page ![]() P2.0/ACLK/A0/CA2 P2.1/TAINCLK/ SMCLK/A1/CA3 Direction 0: Input 1: Output P2SEL.x P2DIR.x P2IN.x P2IRQ.x D EN Module X IN Module X OUT P2OUT.x Interrupt Edge Select Q EN Set P2SEL.x P2IES.x P2IFG.x P2IE.x DVSS DVCC P2REN.x Pad Logic 1 1 0 1 0 1 0 Bus Keeper EN CAPD.x From Comparator_A To Comparator_A INCHx = y To ADC10 ADC10AE0.y 56 MSP430F2132-EP SLAS913A – JULY 2013 – REVISED AUGUST 2013 www.ti.com Product Folder Links: MSP430F2132-EP Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated (1) X = Don't care 6.5 Port P2 Pin Schematic: P2.0 and P2.1, Input/Output With Schmitt Trigger Table 20. Port P2 (P2.0 and P2.1) Pin Functions PIN NAME (P2.x) x FUNCTION CONTROL BITS AND SIGNALS(1) ADC10AE0.y CAPD.x P2DIR.x P2SEL.x P2SEL2.x = 0 P2.0/ACLK/A0/CA2 0 P2.0 (I/O) 0 0 I: 0; O: 1 0 ACLK 0 0 1 1 A0 1 0 X X CA2 0 1 X X P2.1/TAINCLK/ SMCLK/A1/CA3 1 P2.1 (I/O) 0 0 I: 0; O: 1 0 Timer0_A3.TAINCLK, Timer1_A2.TAINCLK 0 0 0 1 SMCLK 0 0 1 1 A1 1 0 X X CA3 0 1 X X |
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