V62SLASH13624-01XE-R datasheet(6/77 Pages) TI1

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General-Purpose Register

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R12

R13

General-Purpose Register

R10

R11

General-Purpose Register

R14

R15

MSP430F2132-EP

SLAS913A – JULY 2013 – REVISED AUGUST 2013

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4 Short-Form Description

4.1 CPU

The MSP430F2132 CPU has a 16-bit RISC architecture that is highly transparent to the application. All

operations, other than program-flow instructions, are performed as register operations in conjunction with seven

addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register

operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant

generator respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses and can be handled with all

instructions.

4.2 Instruction Set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can

operate on word and byte data. Table 1 shows examples of the three types of instruction formats; Table 2 shows

the address modes.

Table 1. Instruction Word Formats

INSTRUCTION FORMAT

EXAMPLE

OPERATION

Dual operands, source-destination

ADD R4,R5

R4 + R5

→ R5

Single operands, destination only

CALL R8

→ (TOS), R8 → PC

Relative jump, unconditional or conditional

JNE

Jump-on-equal bit = 0

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