V62SLASH13624-01XE-R datasheet(41/77 Pages) TI1

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MSP430F2132-EP

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SLAS913A – JULY 2013 – REVISED AUGUST 2013

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(1)

The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the

dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

(2)

The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3)

Under this condition, the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply

current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.

(4)

The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(5)

The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

(6)

Not ensured for TA > 105°C.

5.32 10-Bit ADC, External Reference

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

UNIT

VeREF+

Positive external reference input

voltage range(2)

VeREF+ > VeREF-,

SREF1 = 1, SREF0 = 0

1.4

VCC

VeREF- ≤ VeREF+ ≤ (VCC - 0.15 V),

SREF1 = 1, SREF0 = 1(3)

1.4

VeREF-

Negative external reference input

voltage range(4)

VeREF+ > VeREF-

1.2

ΔVeREF

Differential external reference

input voltage range

ΔVeREF = VeREF+ - VeREF-

VeREF+ > VeREF-

(5)

1.4

VCC

IVeREF+

Static input current into VeREF+

(6)

0 V

≤ VeREF+ ≤ VCC,

SREF1 = 1, SREF0 = 0

2.2 V, 3 V

±1

µA

0 V

≤ VeREF+ ≤ VCC - 0.15 V ≤ 3 V,

SREF1 = 1, SREF0 = 1 (3)

IVeREF-

Static input current into VeREF-

(6)

0 V

≤ VeREF- ≤ VCC

2.2 V, 3 V

±1

µA

(1)

Not ensured for TA > 105°C.

(2)

The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already

settled.

5.33 10-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

fADC10CLK

ADC10 input clock

frequency

For specified performance of

ADC10 linearity parameters

ADC10SR = 0

2.2 V, 3 V

0.45

6.3

MHz

ADC10SR = 1

0.45

1.5

fADC10OSC

ADC10 built-in oscillator

frequency

ADC10DIVx = 0, ADC10SSELx = 0,

fADC10CLK = fADC10OSC

2.2 V, 3 V

3.7

6.3

MHz

tCONVERT

Conversion time

ADC10 built-in oscillator, ADC10SSELx = 0,

fADC10CLK = fADC10OSC

2.2 V, 3 V

2.06

4.00

µs

fADC10CLK from ACLK, MCLK or SMCLK,

ADC10SSELx

≠ 0

13 × ADC10DIVx ×

1 / fADC10CLK

tADC10ON

Turn on settling time of

the ADC(1)

See (2)

100

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