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V62/13624-01XE-R 数据表(PDF) 53 Page - Texas Instruments |
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V62/13624-01XE-R 数据表(HTML) 53 Page - Texas Instruments |
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53 / 77 page ![]() Direction 0: Input 1: Output P1SEL.x P1DIR.x P1IN.x P1IRQ.x Module X IN Timer0_A3 output P1OUT.x Interrupt Edge Select Q EN Set P1SEL.x P1IES.x P1IFG.x P1IE.x DVSS DVCC P1REN.x Pad Logic 1 1 0 0 1 1 0 Bus Keeper EN P1.1/TA0_0/TA0_1 P1.2/TA1_0 P1.3/TA2_0 D EN 53 MSP430F2132-EP www.ti.com SLAS913A – JULY 2013 – REVISED AUGUST 2013 Product Folder Links: MSP430F2132-EP Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated 6.2 Port P1 Pin Schematic: P1.1 to P1.3, Input/Output With Schmitt Trigger Table 17. Port P1 (P1.1 to P1.3) Pin Functions PIN NAME (P1.x) x FUNCTION CONTROL BITS AND SIGNALS P1DIR.x P1SEL.x P1SEL2.x P1.1/TA0.0/TA1.0 1 P1.1 (I/O) I: 0; O: 1 0 0 Timer0_A3.CCI0A, Timer1_A2.CCI0A 0 1 0 Timer0_A3.TA0 1 1 0 P1.2/TA0.1 2 P1.2 (I/O) I: 0; O: 1 0 0 Timer0_A3.CCI1A 0 1 0 Timer0_A3.TA1 1 1 0 P1.3/TA0.2 3 P1.3 (I/O) I: 0; O: 1 0 0 Timer0_A3.CCI2A 0 1 0 Timer0_A3.TA2 1 1 0 |
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