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GD5F2GQ4RF9JS 数据表(PDF) 39 Page - GigaDevice Semiconductor (Beijing) Inc.

部件名 GD5F2GQ4RF9JS
功能描述  SPI(x1/x2/x4) NAND Flash
PDF  57 Pages
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制造商  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
网页  http://www.gigadevice.com/
标志 GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD5F2GQ4RF9JS 数据表(HTML) 39 Page - GigaDevice Semiconductor (Beijing) Inc.

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SPI(x1/x2/x4) NAND Flash
2G
39
13.2.2 Hardware RESET Setting
a)
LGA8 package
For the LGA8 package, RESET#, HOLD# and data IO3 share the same pin7. The pin7 can be configured as any of
the three functions depending on the status register setting. When QE=0, HOLDB/RST=1, the pin7 acts as a RESET#
pin. When QE=1 or QE=0 HOLDB/RST=0, the pin7 will be configured as the other functions and Hardware Reset
function can’t be used.
QE and HOLDB/RST registers can be set by Set Feature command (see Table13-2). QE can be set by Set Feature
command when address is B0H and HOLDB/RST can be set by Set Feature command when address is D0H. Both of
them can be read out by Get Feature command with related address. Through reading the status registers, users could
know the value and infer which function is supported on the pin7.
By default QE and HOLDB/RST registers are both 0 after power-on-reset or hardware reset.
Table13-2. Features Settings
Register Addr.
7
6
5
4
3
2
1
0
Protection
A0H
BRWD
Reserved
BP2
BP1
BP0
INV
CMP
Reserved
Feature
B0H
OTP_PRT
OTP_EN
Reserved
ECC_EN
Reserved
Reserved
Reserved
QE
Status
C0H
Reserved
ECCS2
ECCS1
ECCS0
P_FAIL
E_FAIL
WEL
OIP
Feature
D0H
HOLDB/RST
DS_IO[1]
DS_IO[0]
Reserved
Reserved
Reserved
Reserved
Reserved
b)
BGA24 package
For BGA24 package (see Figure2-1), a dedicated RESET# pin is provided and it is independent of QE bit setting. At
the same time, HOLDB/RST register is not existed in BGA24, and the corresponding bit in command Set/Get Feature
with address D0H is reserved.
Table13-3. Features Settings
Register Addr.
7
6
5
4
3
2
1
0
Protection
A0H
BRWD
Reserved
BP2
BP1
BP0
INV
CMP
Reserved
Feature
B0H
OTP_PRT
OTP_EN
Reserved
ECC_EN
Reserved
Reserved
Reserved
QE
Status
C0H
Reserved
ECCS2
ECCS1
ECCS0
P_FAIL
E_FAIL
WEL
OIP
Feature
D0H
Reserved
DS_IO[1]
DS_IO[0]
Reserved
Reserved
Reserved
Reserved
Reserved



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