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GD5F2GQ4RF9JS 数据表(PDF) 44 Page - GigaDevice Semiconductor (Beijing) Inc.

部件名 GD5F2GQ4RF9JS
功能描述  SPI(x1/x2/x4) NAND Flash
PDF  57 Pages
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制造商  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
网页  http://www.gigadevice.com/
标志 GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD5F2GQ4RF9JS 数据表(HTML) 44 Page - GigaDevice Semiconductor (Beijing) Inc.

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SPI(x1/x2/x4) NAND Flash
2G
44
14.5 Internal ECC
The serial device offers data corruption protection by offering optional internal ECC.READs and PROGRAMs with internal
ECC can be enabled or disabled by setting feature bit ECC_EN. ECC is enabled after device power up, so the default
READ
and PROGRAM commands operate with internal ECC in the “active” state. To enable/disable ECC, perform the
following command sequence:
• Issue the SET FEATURES command (1FH).
• Set the feature bit ECC_EN as you want:
1.
To enable ECC, Set ECC_EN to 1.
2.
To disable ECC, Clear ECC_EN to 0.
During a PROGRAM operation, the device calculates an ECC code on the 2k page in the cache register, before the page
is written to the NAND Flash array.
During a READ operation, the page data is read from the array to the cache register, where the ECC code is calculated
and compared with the ECC code value read from the array. If error bits are detected, the error is corrected in the cache
register. Only corrected data is output on the I/O bus. The ECC status bit indicates whether or not the error correction was
successful. The ECC Protection table below shows the ECC protection scheme used throughout a page.
With internal ECC, the user must accommodate the following:
• Spare area definitions provided in the ECC Protection table below.
• ECC can protect according main and spare areas. WRITEs to the ECC area are ignored.
Table14-6. ECC Protection and Spare Area
Min Byte Address
Max Byte Address
ECC Protected
Area
Description
000h
1FFh
Yes
Main 0
User data 0
200h
3FFh
Yes
Main 1
User data 1
400h
5FFh
Yes
Main 2
User data 2
600h
7FFh
Yes
Main 3
User data 3
800h
80Fh
Yes
Spare 0
User meta data 0(1)
810h
81Fh
Yes
Spare 1
User meta data 1
820h
82Fh
Yes
Spare 2
User meta data 2
830h
83Fh
Yes
Spare 3
User meta data 3
840h
87Fh
Yes
Spare Area
Internal ECC parity data
Note:
1.
800H is reserved for initial bad block mark, and please check the initial bad block mark with internal ECC off.
2.
When Internal ECC is enabled,user cannot program the Address 840H~87FH but user can read the Address
840H~87FH.
3.
When Internal ECC is disabled, the whole page area is open for user.



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