GD5F2GQ4RF9JS datasheet(11/57 Pages) GIGADEVICE

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SPI(x1/x2/x4) NAND Flash

DEVICE OPERATION

5.1 SPI Modes

SPI NAND supports two SPI modes:

• CPOL = 0, CPHA = 0 (Mode 0)

• CPOL = 1, CPHA = 1 (Mode 3)

Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK for both modes. All timing

diagrams shown in this data sheet are mode 0. See Figure5-1 for more details.

Figure5-1. SPI Modes Sequence Diagram

CS#

SCLK

CPOL CPHA

MSB

LSB

MSB

LSB

Note: While CS# is HIGH, keep SCLK at VCC or GND (determined by mode 0 or mode 3).

Standard SPI

SPI NAND Flash features a standard serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select

(CS#), Serial Data Input (SI) and Serial Data Output (SO).

Dual SPI

SPI NAND Flash supports Dual SPI operation when using the x2 and dual IO commands. These commands allow

data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command

the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1.

Quad SPI

SPI NAND Flash supports Quad SPI operation when using the x4 and Quad IO commands. These commands allow

data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command

the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1, and WP# and HOLD#/RESET# pins become SIO2 and

SIO3.

GD5F2GQ4RF9JS 数据表(PDF) 11 Page - GigaDevice Semiconductor (Beijing) Inc.