GD5F2GQ4RF9JS datasheet(9/57 Pages) GIGADEVICE

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SPI(x1/x2/x4) NAND Flash

ARRAY ORGANIZATION

Each device has

Each block has

Each page has

256M+16M

128K+8K

2K+128

bytes

2048 x 64

pages

2048

blocks

Figure3-1. Array Organization

2048

128

2048

128

1 block

1 block = (2K + 128 bytes) x 64 pages

= (128K + 8K) bytes

1 page

= (2K + 128 bytes)

Cache Register

Data Register

Per device:

2Gb: 2048blocks

1 device:

For 2Gb = (128K + 8K) bytes x 2048 blocks

= 2Gb

Internal ECC = OFF

2048

1 block

1 block = (2K + 64 bytes) x 64 pages

= (128K + 4K) bytes

1 page

= (2K + 64 bytes)

Cache Register

Data Register

Per device:

2Gb: 2048blocks

1 device:

For 2Gb = (128K + 4K) bytes x 2048 blocks

= 2Gb

Internal ECC= ON

Note:

1.When Internal ECC is enabled，user can program the first 64 bytes of the entire 128 bytes spare area and

the last 64 bytes of the whole spare area cannot be programed，user can read the entire 128 Byte spare area.

2.When Internal ECC is disabled，user can read and program the entire 128 bytes spare area.

GD5F2GQ4RF9JS 数据表(PDF) 9 Page - GigaDevice Semiconductor (Beijing) Inc.

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GD5F2GQ4RF9JS 数据表(PDF) 9 Page - GigaDevice Semiconductor (Beijing) Inc.

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