MT7697D datasheet(22/84 Pages) ETC2

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MT7697D

Internet-of-Things Wireless Connectivity

Page 22 of 84

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

The cache controller provides the user ways to perform cache operations including invalidate

single/all cache lines as well as flush one/all cache lines.

To facilitate tuning the system performance, the cache controller can record the statistics of the

cache hit count and the number of cacheable memory access. Cache hit rate can be obtained by

dividing the cache hit count by the number of memory access.

2.4.3

Bus Fabric

MT7697D implements AHB/APB bus fabric to connect the MCU, memory, IO peripherals, and the

radio subsystem.



ILM/DLM: Instruction Local Memory / Data Local Memory, the zero-wait-state local

memory for Radio MCU.



Wi-Fi HIF: The data interface to Wi-Fi Packet switch engine.



BT FIFO I/F: The control/data interface to Bluetooth subsystem.

ARM Cortex M4

Cache

Controller

TCM/Cache

(96KB)

CM4 AHB bus

Generic DMA

SPI flash

APB

bridge

APB2 bus

Wi-Fi HIF

UART1

UART2

I2C-1

I2C-2

SPI-M

I2S

BT FIFO

I/F

AUX

ADC

TOP &

CM4

CONFIG

GPT

WDT

Interface to radio subsystem

Indium peripherals

APB

bridge

SYSRAM_

CM4

(256KB)

APB1 bus

ILM/DLM

PWM

XIP

AHB mux

ICODE

DCODE

SYSTEM

Asyncrhrous AHB-2-

AHB bridge

(N9 bus to CM4 bus)

Asyncrhrous AHB-2-

AHB bridge

(CM4 bus to N9 bus)

APB

bridge

APB0 bus

TCM ROM

N9 AHB bus

GDMA

CONFIG

Crypto

Engine

Figure 2-6. CM4 Subsystem – Bus Fabric

The AHB bus arbitration adopts round-robin scheme.

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