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ADN2525ACPZ-R2 数据表(PDF) 3 Page - Analog Devices |
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ADN2525ACPZ-R2 数据表(HTML) 3 Page - Analog Devices |
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3 / 16 page ![]() ADN2525 Rev. 0 | Page 3 of 16 SPECIFICATIONS VCC = VCCMIN to VCCMAX, TA = −40°C to +85°C, 50 Ω differential load resistance, unless otherwise noted. Typical values are specified at 25°C, IMOD = 40 mA. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments BIAS CURRENT (IBIAS) Bias Current Range 10 100 mA Bias Current while ALS Asserted 100 µA ALS = high Compliance Voltage1 0.6 VCC – 1.2 V IBIAS = 100 mA 0.6 VCC – 0.8 V IBIAS = 10 mA MODULATION CURRENT (IMODP, IMODN) Modulation Current Range 10 80 mA diff RLOAD = 5 Ω to 50 Ω differential Modulation Current while ALS Asserted 0.5 mA diff ALS = high Rise Time (20% to 80%)2, 3 24 32.5 ps Fall Time (20% to 80%) 2 , 3 24 32.5 ps Random Jitter 2 , 3 0.4 0.9 ps rms Deterministic Jitter3, 4 7.2 12 ps p-p Differential |S22| −10 dB 5 GHz < F < 10 GHz, Z0 = 50 Ω differential −14 dB F < 5 GHz, Z0 = 50 Ω differential Compliance Voltage 1 VCC − 1.1 VCC + 1.1 V DATA INPUTS (DATAP, DATAN) Input Data Rate 10.7 Gbps NRZ Differential Input Swing 0.4 1.6 V p-p diff Differential ac-coupled Differential |S11| −16.8 dB F < 10 GHz, Z0 = 100 Ω differential Input Termination Resistance 85 100 115 Ω Differential BIAS CONTROL INPUT (BSET) BSET Voltage to IBIAS Gain 75 100 120 mA/V BSET Input Resistance 800 1000 1200 Ω MODULATION CONTROL INPUT (MSET) MSET Voltage to IMOD Gain 70 88 110 mA/V See Figure 29 MSET Input Resistance 800 1000 1200 Ω BIAS MONITOR (IBMON) IBMON to IBIAS Ratio 10 µA/mA Accuracy of IBIAS to IBMON Ratio −5.0 +5.0 % 10 mA ≤ IBIAS < 20 mA, R IBMON = 1 kΩ −4.0 +4.0 % 20 mA ≤ IBIAS < 40 mA, R IBMON = 1 kΩ −2.5 +2.5 % 40 mA ≤ IBIAS < 70 mA, R IBMON = 1 kΩ −2 +2 % 70 mA ≤ IBIAS < 100 mA, R IBMON = 1 kΩ AUTOMATIC LASER SHUTDOWN (ALS) VIH 2.4 V VIL 0.8 V IIL −20 +20 µA IIH 0 200 µA ALS Assert Time 10 µs Rising edge of ALS to fall of IBIAS and IMOD below 10% of nominal; see Figure 2 ALS Negate Time 10 µs Falling edge of ALS to rise of IBIAS and IMOD above 90% of nominal; see Figure 2 POWER SUPPLY VCC 3.07 3.3 3.53 V ICC5 39 45 mA VBSET = VMSET = 0 V ISUPPLY6 157 176 mA VBSET = VMSET = 0 V. ISUPPLY = ICC + IMODP + IMODN 1 Refers to the voltage between the pin for which the compliance voltage is specified and GND. 2 The pattern used is composed by a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps. 3 Measured using the high speed characterization circuit shown in Figure 3. 4 The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate. 5 Only includes current in the ADN2525 VCC pins. 6 Includes current in ADN2525 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the section for total supply current calculation. Power Consumption |
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