ADN2525

Rev. 0 | Page 9 of 16

THEORY OF OPERATION

As shown in Figure 1, the ADN2525 consists of an input stage

and two voltage controlled current sources for bias and modula-

tion. The bias current is available at the IBIAS pin. It is controlled

by the voltage at the BSET pin, and can be monitored at the

IBMON pin. The differential modulation current is available at

the IMODP and IMODN pins. It is controlled by the voltage at

the MSET pin. The output stage implements the active back-

match circuitry for proper transmission line matching and

power consumption reduction. The ADN2525 can drive a load

having differential resistance ranging from 5 Ω to 50 Ω. The

excellent back-termination in the ADN2525 absorbs signal

reflections from the TOSA end of the output transmission lines,

enabling excellent optical eye quality to be achieved even when

the TOSA end of the output transmission lines is significantly

mis-terminated.

INPUT STAGE

The input stage of the ADN2525 converts the data signal applied

to the DATAP and DATAN pins to a level that ensures proper

operation of the high speed switch. The equivalent circuit of the

input stage is shown in Figure 17.

VCC

50

Ω

50

Ω

VCC

DATAP

DATAN

VCC

Figure 17. Equivalent Circuit of the Input Stage

The DATAP and DATAN pins are terminated internally with a

100 Ω differential termination resistor. This minimizes signal

reflections at the input, which could otherwise lead to degrada-

tion in the output eye diagram. It is not recommended to drive

the ADN2525 with single-ended data signal sources.

The ADN2525 input stage must be ac-coupled to the signal

source to eliminate the need for matching between the common-

mode voltages of the data signal source and the input stage of

the driver (see Figure 18). The ac-coupling capacitors should

have an impedance less than 50 Ω over the required frequency

range. Generally this is achieved using 10 nF to 100 nF capacitors.

ADN2525

DATAP

DATAN

C

C

50

Ω

50

Ω

DATA SIGNAL SOURCE

Figure 18. AC-Coupling the Data Source to the

ADN2525 Data Inputs

BIAS CURRENT

The bias current is generated internally using a voltage-to-current

converter consisting of an internal operational amplifier and a

transistor as shown in Figure 19.

GND

200

Ω

800

Ω

2

Ω

RR

VCC

IBMON

BSET

ADN2525

200

Ω

IBIAS

Figure 19. Voltage-to-Current Converter Used to Generate IBIAS

The voltage-to-current conversion factor is set at 100 mA/V by

the internal resistors, and the bias current is monitored using a

current mirror with a gain equal to 1/100. By connecting a 1 kΩ

resistor between IBMON and GND, the bias current can be

monitored as a voltage across the resistor. A low temperature

coefficient precision resistor must be used for the IBMON

ances, or drift in its value over temperature, contributes to the

overall error budget for the IBIAS monitor voltage. If the IBMON

voltage is being connected to an ADC for A/D conversion,

due to voltage drops on the ground plane.