ADN2525

Rev. 0 | Page 13 of 16

APPLICATIONS INFORMATION

TYPICAL APPLICATION CIRCUIT

Figure 33 shows the typical application circuit for the ADN2525.

The dc voltages applied to the BSET and MSET pins control the

bias and modulation currents. The bias current can be monitored

as a voltage drop across the 1 kΩ resistor connected between

the IBMON pin and GND. The ALS pin allows the user to turn

on/off the bias and modulation currents, depending on the logic

level applied to the pin. The data signal source must be connected

to the DATAP and DATAN pins of the ADN2525 using 50 Ω

transmission lines. The modulation current outputs, IMODP

and IMODN, must be connected to the load (TOSA) using 50 Ω

differential (25 Ω single-ended) transmission lines. Table 5

shows recommended components for the ac-coupling interface

between the ADN2525 and TOSA. For up-to-date component

recommendations, contact your sales representative.

Table 5.

Component

Value

Description

R1, R2

36 Ω

0603 size resistor

R3, R4

200 Ω

0603 size resistor

C3, C4

100 nF

0603 size capacitor,

Phycomp 223878615649

L2, L3, L6, L7

82 nH

0402 size inductor,

Murata LQW15AN82NJ0

L1, L4, L5, L8

10 µH

0603 size inductor,

Murata LQM21FN100M70L

LAYOUT GUIDELINES

Due to the high frequencies at which the ADN2525 operates,

care should be taken when designing the PCB layout to obtain

optimum performance. Controlled impedance transmission

lines must be used for the high speed signal paths. The length

of the transmission lines must be kept to a minimum to reduce

losses and pattern-dependent jitter. The PCB layout must be

symmetrical, both on the DATAP, DATAN inputs, and on the

IMODP, IMODN outputs, to ensure a balance between the

differential signals. All VCC and GND pins must be connected

to solid copper planes by using low inductance connections.

When the connections are made through vias, multiple vias can

be connected in parallel to reduce the parasitic inductance.

Each GND pin must be locally decoupled with high quality

capacitors. If proper decoupling cannot be achieved using a

single capacitor, the user can use multiple capacitors in parallel

for each GND pin. A 20 µF tantalum capacitor must be used as

general decoupling capacitor for the entire module. For

guidelines on the surface-mount assembly of the ADN2525,

consult the Amkor Technology® application note “Application

Notes for Surface Mount Assembly of Amkor’s

MicroLeadFrame® (MLF) Packages.”

MSET

NC1

ALS

GND

BSET IBMON IBIAS

GND

VCC

DATAP

DATAN

VCC

VCC

IMODP

IMODN

VCC

DATAP

DATAN

C1

C2

MSET

BSET

R5

1k

Ω

ADN2525

GND

VCC

GND

VCC

TOSA

C4

C7

20

µF

L2

L1

R1

+3.3V

VCC

VCC

VCC

VCC

VCC

TP1

C5

10nF

GND

GND

VCC

C6

10nF

GND

ALS

L7

L8

R4

L6

L5

R3

VCC

L3

L4

R2

VCC

C3

GND

Figure 33. Typical ADN2525 Application Circuit