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56F8167 数据表(PDF) 144 Page - Freescale Semiconductor, Inc |
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56F8167 数据表(HTML) 144 Page - Freescale Semiconductor, Inc |
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144 / 184 page ![]() 56F8367 Technical Data, Rev. 7.0 144 Freescale Semiconductor Preliminary Table 10-8 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Disabled (OCR_DIS = High) Mode IDD_Core IDD_IO 1 1. No Output Switching IDD_ADC IDD_OSC_PLL Test Conditions RUN1_MAC 150mA 13 µA50mA 2.5mA • 60MHz Device Clock • All peripheral clocks are enabled • All peripherals running • Continuous MAC instructions with fetches from Data RAM • ADC powered on and clocked Wait3 86mA 13 µA70µA2.5mA • 60MHz Device Clock • All peripheral clocks are enabled • ADC powered off Stop1 950 µA13µA0µA165µA • 8MHz Device Clock • All peripheral clocks are off • ADC powered off • PLL powered off Stop2 100 µA13µA0µA155µA • External Clock is off • All peripheral clocks are off • ADC powered off • PLL powered off Table 10-9. Regulator Parameters Characteristic Symbol Min Typical Max Unit Unloaded Output Voltage (0mA Load) VRNL 2.25 — 2.75 V Loaded Output Voltage (200 mA load) VRL 2.25 — 2.75 V Line Regulation @ 250 mA load (VDD33 ranges from 3.0 to 3.6) VR 2.25 — 2.75 V Short Circuit Current ( output shorted to ground) Iss — — 700 mA Bias Current I bias —5.8 7 mA Power-down Current Ipd —0 2 µA Short-Circuit Tolerance (output shorted to ground) TRSC — — 30 minutes |
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