MTC20136

14/25

Figure 3. Access to MTC20135, MTC20455

SDRAM

The SDRAM interface allows a glue-less interconnection of 1 SDRAM. Following features are provided for

SDRAM access.

– 16 bit databus and 12 bit address bus.

– control signals : S_nCS, S_nRAS, S_nCAS, S_nWE, S_DQM[1:0

Control signal timing

All SDRAM actions are triggered at the rising edge of its clock. Timing diagrams for a burst of four 16-bit

accesses to 16-bit SDRAM (Figure 3 and Figure 4) show the basic behavior of the control signals.

Figure 4. SDRAM read access (CAS latency = 3; Burst length = 4)

E_CLK

Ta

Tw

Td

Tr

Ti

Ta

Tw

Td

Tr

notCSi

ALE

E_D

Add 1

Read

Access

Write

Access

Add 2

Dout

EBI

Din

notRDYRCV

W/notR

EAact

EArw

EApre

S_clk

S_nCS

S_nRAS

S_nCAS

S_nWE

S_DQM[1:0]

S_A[11:0]

S_Q[15:0]