MTC20136

20/25

Table 8. write cycle timing in parallel modes 0 and 1

Read cycle timing

Figure 9. Ctrl-E interface: read cycle timing in parallel modes 0 and 1

Table 9. read cycle timing in parallel modes 0 and 1

Symbol

Description

Min

Max

Unit

t1

C_A Setup to C_notDS (C_notWr) low

0

ns

t2

C_notCS, C_Rd/notWr setup to C_notDS (C_notWr) low

0

ns

t3

C_notDS (C_notWr) pulse width

215

ns

t4

C_D setup to C_notDS (C_notWr) high

15

ns

t5

C_A, C_D hold from C_notDS (C_notWr) high

5

ns

t6

C_notDtAck (C_notRdy) valid from C_notDS (C_notWr) low

15

ns

t7

C_notDtAck (C_notRdy) tri-state from C_notDS (C_notWr) high

15

ns

t8

C_notCS, C_Rd/notWr hold from C_notDS (C_notWr) high

0

ns

t9

C_notCS high to C_notCS Low

100

ns

Symbol

Description

Min

Max

Unit

t1

C_A Setup to C_notDS (C_notRd) low

0

ns

t2

C_notCS, C_Rd/notWr setup to C_notDS (C_notRd) low

0

ns

t3

C_notDS (C_notRd) pulse width

215

ns

t4

C_D valid from C_notDtAck (C_notRdy) low

10

ns

t5

C_A, hold from C_notDS (C_notRd) high

0

ns

t6

C_notDtAck (C_notRdy) valid from C_notDS (C_notRd) high

15

ns

t7

C_notDtAck (C_notRdy) tri-state from C_notDS (C_notRd) high

10

ns

t8

C_notCS, C_Rd/notWr hold from C_notDS (C_notRd) high

10

ns

t9

Data tri-state from C_notDS (C_notRd) high

90

100

ns

t10

Data tri-state from C_notCS high

5

15

ns

t11

C_notCS high to C_notCS low (Min. time between 2 Accesses)

100

ns

t1

C_A[8:0]

C_D[7:0]

C_notCS

C_Rd/notWr

C_notDS

C_notDtAck

C_notRd

Mode 0

C_notWr

C_notRdy

t2

t7

t6

t3

t8

t4

t5

t11

t10

t9

Mode 1