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MTC20136

Generic Parallel Interface

The two parallel bus modes differ only in the definition of 3 control signals: busmode 0 provides a read/

write selector, a data strobe and a ready acknowledge. Busmode 1 provides a read strobe, a write strobe

and a ready acknowledge. The signal definition is shown in following table:

Table 7. Ctrl-E interface signals in parallel interface modes

Write cycle timing

Figure 8. Ctrl-E interface: write cycle timing in parallel modes 0 and 1

Signal name

Type

Function

PIN

C_A[8:0]

I

address bus

C_A[8:0]

C_D[7:0]

IO

byte wide bidirectional data bus

C_D[7:0]

C_notCS

I

chip select

C_notCS

C_notInt

OZ

Interrupt output, derived from CtrleInt1 signal from

Mailbox : low when CtrleInt1 is low, else tri-stated

C_notInt

Mode 0 : Motorola-compatible mode

C_Mode[1:0]

I

C_Mode[1:0]

C_Rd/notWr

I

read access if 1, write access if 0

C_notWr

C_notDS

I

Data Strobe

C_notRd

C_notDtAck

OZ

Bus cycle ready indication, indicates that data on bus

can be sampled or removed

C_notRdy

Mode 1 : Intel-compatible mode

C_Mode[1:0]

I

C_Mode[1:0]

C_notWr

I

write cycle indication

C_notWr

C_notRd

I

read cycle indication

C_notRd

C_notRdy

OZ

Bus cycle ready indication, indicates that data on bus

can be sampled or removed, same as in mode 0

C_notRdy

t1

C_A[8:0]

C_D[7:0]

C_notCS

C_Rd/notWr

C_notDS

C_notDtAck

C_notWr

Mode 0

C_notRd

C_notRdy

t2

t7

t6

t3

t8

t4

t5

t9

Mode 1