MTC20136

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The table below describes the pins, organized per interface. Some of these pins have a multiple function-

ality. In this case both functionalities are mentioned.

Name

I/O Type

Description

External Bus Interface

E_A[19:16]

O

Address bus MSBs

E_A[15:0]

I/O

Address bus LSBs / Testbus MSBs

E_D[15:0]

I/O

Data bus / Testbus LSBs

E_CLK

O

EBI clock (ASIC Access)

E_ALE

O

Address latch enable (ASIC Access)

E_nCS_0

O

Chip select signal (Memory Bank 0)

E_nCS_1

O

Chip select signal (Memory Bank 1)

E_nCS_S

O

Chip select signal (SDRAM)

E_nCS_4

O

Chip select signal (ASIC 1)

E_nCS_5

O

Chip select signal (ASIC 2)

E_nCS_6

O

Chip select signal (ASIC 3)

E_nCS_7

O

Chip select signal (ASIC 4)

E_nRDYRCV

I

Data acknowledge

E_nOE

O

Output enable

E_nWE0

O

Write enable LSB / W/notR indication

E_nWE1

O

Write enable MSB

Clock Bus Interface

CLK_IN

I

MTC20136 Master clock

Parallel Port Interface

PA[0]

I/O

Port A bit[0]

PA[1]

I/O

Port A bit[1]

UART1 Interface

RSTXD1

O

Serial TX port

RSRXD1

I

Serial RX port

UART2 Interface

RSTXD2

O

Serial TX port

RSRXD2

I

Serial RX port

Interrupt Interface

EIT_0

I

External interrupt lines

EIT_1

I

External interrupt lines

EIT_2

I

External interrupt lines

EIT_3

I

External interrupt lines

JTAG Interface

nTRST

I-PU

Reset JTAG interface

TCK

I-PU

JTAG clock

TDI

I-PU

Test Data In

TMS

I-PU

Test Mode Select

TDO

O

Test Data Out

Reset Interface

RESETN

I

Reset signal (Active High)

Boot Interface

TROM

I

Boot from ROM select