CS5321/22

6

DS454F2

Notes: 15. Guaranteed by design, characterization, or test.

16. If MCLK is removed, the modulator will enter the power down mode.

17. Excludes MCLK input. MCLK should be driven with a signal having rise and fall times of 25 ns or faster.

Parameter

Symbol

Min

Typ

Max

Units

MCLK Frequency

(Note 16)

0.250

1.024

1.2

MHz

MCLK Duty Cycle

40

-

60

%

MCLK Jitter (In-band)

-

-

300

ps

Rise Times:

Any Digital Input

(Note 17)

Any Digital Output

-

-

-

50

100

200

ns

ns

Fall Times:

Any Digital Input

(Note 17)

Any Digital Output

-

-

-

50

100

200

ns

ns

MSYNC Setup Time to MCLK rising

20

-

-

ns

MSYNC Hold Time after MCLK rising

20

-

-

ns

MCLK rising to Valid MFLG

-140

255

ns

MCLK rising to Valid MDATA

-170

300

ns

4.0 V

1.0 V

4.6 V

0.4 V

Figure 1. Rise and Fall Times

MF LG

MD A T A

t mdv

t mdv

VA L ID DAT A

VA L ID DA T A

MC L K

t mss

MS Y N C

t mfh

t msh

Figure 2. CS5321 Interface Timing, HBR=1