CS5321 datasheet(18/36 Pages) CIRRUS

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CS5321/22

DS454F2

2.1 Analog Input

The CS5321 modulator uses a switched capacitor

architecture for its signal and voltage reference in-

puts. The signal input uses three pins; AINR, AIN+,

and AIN-. The AIN- pin acts as the return pin for

the AINR and AIN+ pins. The AINR pin is a

switched capacitor "rough charge" input for the

AIN+ pin. The input impedance for the rough

charge pin (AINR) is 1/fC where f is two times the

modulator sampling clock rate and C is the internal

sampling capacitor (about 40 pF). Using a 1.024

MHz master clock (HBR = 1) yields an input im-

pedance of about 1/(512 kHz)X(40 pF) or about 50

Ω. Internal to the chip the rough charge input pre-

charges the sampling capacitor used on the AIN+

input, therefore the effective input impedance on

the AIN+ pin is orders of magnitude above the im-

pedance seen on the AINR pin.

The analog input structure inside the VREF+ pin is

very similar to the AINR pin but includes addition-

al circuitry whose operating current can change

over temperature and from device to device. There-

fore, if gain accuracy is important, the VREF+ pin

should be driven from a low source impedance.

The current demand of the VREF+ pin will produce

a voltage drop of approximately 45 mV across the

200

Ω source resistor of Figure 20 and Figure 21

Option A with MCLK = 1.024 MHz, HBR = 1, and

temperature = 25

°C.

When the CS5321 modulator is operated with a 4.5

V reference it will accept a 9 V p-p input signal, but

modulator loop stability can be adversely affected

by high frequency out-of-band signals. Therefore,

input signals must be band-limited by an input fil-

ter. The -3 dB corner of the input filter must be

equal to the modulator sampling clock divided by

64. The modulator sampling clock is MCLK/4

when HBR = 1 or MCLK/8 when HBR = 0. With

MCLK = 1.024 MHz, HBR = 1, the modulator

sampling clock is 256 kHz which requires an input

filter with a -3 dB corner of 4 kHz. The bandlimit-

ing may be accomplished in an amplifier stage

ahead of the CS5321 modulator or with the RC in-

put filter at the AIN+ and AINR input pins. The RC

filter at the AIN+ and AINR pins is recommended

to reduce the "charge kick" that the driving ampli-

fier sees as the switched capacitor sampling is per-

formed.

Figure 20 illustrates the CS5321 and CS5322 sys-

tem connections. The input components on AINR

and AIN+ should be identical values for optimum

performance. In choosing the components the ca-

pacitor should be a minimum of 0.1

µF (C0G di-

electric ceramic preferred). For minimum board

space, the RC components on the AINR input can

be removed, but this will force the driving amplifi-

er to source the full dynamic charging current of

the AINR input. This can increase distortion in the

driving amplifier and reduce system performance.

In choosing the RC filter components, increasing C

and minimizing R is preferred. Increasing C reduc-

es the instantaneous voltage change on the pin, but

may require paralleling capacitors to maintain

smaller size (the recommended 0.1

µF C0G ceram-

ic capacitor is larger than other similar-valued ca-

pacitors with different dielectrics). Larger resistor

values will increase the voltage drop across the re-

sistor as the recharging current charges the

switched capacitor input.

2.2 The OFST Pin

The CS5321 modulator can produce "idle tones"

which occur in the passband when the input signal

is steady state dc signal within about

±50 mV of bipolar zero. In the CS5321 these tones

are about 135 dB down from full scale. The user

can force these idle tones "out-of-band" by adding

100 mV of dc offset to the signal at the AIN input.

Alternately, if the user circuitry has a low offset

voltage such that the input signal is within

±50 mV

of bipolar zero when no AC signal is present, the

OFST pin on the CS5321 can be activated. When

OFST = 1, +100 mV of input referred offset will be

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