CS5321 datasheet(19/36 Pages) CIRRUS

19 / 36 page

CS5321/22

DS454F2

added internal to the CS5321 and guarantee that

any idle tones present will lie out-of-band. The user

should be certain that when OFST is active (OFST

=1) that the offset voltage generated by the user cir-

cuitry does not negate the offset added by the

OFST pin.

2.3 Input Range and Overrange

Conditions

The analog input is applied to the AIN+ and AINR

pins with the AIN- pin connected to GND. The in-

put is fully differential but for proper operation the

AIN- pin must remain at GND potential.

The analog input span is defined by the voltage ap-

plied between the VREF+ and VREF- input pins.

See the Voltage Reference section of this data sheet

for voltage reference requirements.

The modulator is a fourth order delta-sigma and is

therefore conditionally stable. The modulator may

go into an oscillatory condition if the analog input

is overranged. Input signals which exceed either

plus or minus full scale by more than 5 % can intro-

duce instability in the modulator. If an unstable

condition is detected, the modulator will be re-

duced to a first order system until loop stability is

achieved. If this occurs the MFLG pin will transi-

tion from a low to a high and result in an error bit

being set in the CS5322. The input signal must be

reduced to within the full scale range of the con-

verter for at least 32 MCLK cycles for the modula-

tor to recover from this error condition.

TDATA

VD+

DGND

+5 V

Digital

Supply

0.01 F

SID

SOD

SCLK

R/W

DRDY

RSEL

ERROR

CSEL

PWDN

USEOR

ORCAL

DECA

DECB

DECC

CLKIN

SYNC

Serial

Data

Interface

Unused logic

inputs must be

connected to

DGND or VD+

CS5322

Control

Hardware

VD+

DGND

+5 V

Digital

Supply

0.01 F

H/S

RESET

GND1

VREF+

Vdd2

Vss2

Vdd1

0.1 F

-5V

Analog

Supply

+5V

Analog

Supply

CS5321

0.1 F

Test

Data

10 F

GND2

Vss1

0.1 F

GND9

GND10

GND8

+4.5V

VREF

0.1 F

µF

TANT.

VREF-

AIN+

0.1 F

Signal

Source

COG

AIN-

AINR

GND5

GND6

GND3

GND4

GND7

402

MSYNC

MFLG

MCLK

MDATA

GND11

OFST

LPWR

HBR

Control

Logic

Clock

Source

MDATA

200

0.1 F

COG

402

Ω

Figure 20. System Connection Diagram

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