CS42448 datasheet(21/70 Pages) CIRRUS

21 / 70 page

DS648PP2

Notes: 16. After powering up the CS42448, RST should be held low after the power supplies and clocks are settled.

17. See Table 10 on page 46 and Table 11 on page 47 for suggested MCLK frequencies.

18. When operating in TDM interface format, VLS is limited to nominal 2.5 V to 5.0 V operation only.

19. ADC - I²S, Left-Justified, Right-Justified interface formats only. DAC - I²S, Left-Justified, Right-Justified

and Time Division Multiplexed interface formats only.

20. “LRCK” and “SCLK” shall refer to the ADC and DAC left/right clock and serial clock, respectively.

Master Mode

Output Sample Rate (LRCK)

All Speed Modes

MCLK / 256

kHz

LRCK Duty Cycle

SCLK Frequency

64 x Fs

MHz

SCLK Duty Cycle

LRCK Edge to SCLK Rising Edge

tlcks

-5

SCLK Falling Edge to ADC_SDOUT Output Valid

tdpd

-35

DAC_SDIN Setup Time Before SCLK Rising Edge

tds

DAC_SDIN Hold Time After SCLK Rising Edge

tdh1

Parameters (Note 20)

Symbol

Min

Max

Units

ADC_SDOUTx

DAC_SDINx

SCLK

LRCK

MSB

dpd

MSB-1

MSB

MSB-1

lcks

Figure 6. Serial Audio Interface Master Mode Timing

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