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CS42448 数据表(PDF) 35 Page - Cirrus Logic |
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CS42448 数据表(HTML) 35 Page - Cirrus Logic |
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35 / 70 page  DS648PP2 35 4.5.5 OLM #2 OLM #2 serial audio interface format operates in single or double-speed mode and will master or slave ADC/DAC_SCLK at 256Fs. 4.5.6 TDM Data is received most significant bit (MSB) first, on the second rising edge of the DAC_SCLK occurring after a DAC_LRCK rising edge. All data is valid on the rising edge of DAC_SCLK. The AIN1 MSB is transmitted early but is guaranteed valid for a specified time after SCLK rises. All other bits are transmitted on the falling edge of ADC_SCLK. Each time slot is 32 bits wide, with the valid data sample left justified within the time slot. Valid data lengths are 16, 18, 20, or 24. ADC/DAC_SCLK must operate at 256Fs. ADC/DAC_LRCK identifies the start of a new frame and is equal to the sample rate, Fs. ADC/DAC_LRCK is sampled as valid on the rising ADC/DAC_SCLK edge preceding the most significant bit of the first data sample and must be held valid for at least 1 ADC/DAC_SCLK pe- riod. NOTE: The ADC does not meet the timing requirements for proper operation in Quad-Speed Mode. Figure 19. One Line Mode #2 Format ADC/DAC_LRCK ADC/DAC_SCLK LSB MSB 24 clks 128 clks LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB MSB 24 clks 24 clks 24 clks 24 clks 24 clks Left Channel Right Channel 24 clks AIN1 24 clks 24 clks 24 clks 24 clks 24 clks ADC_SDOUT1 DAC_SDIN1 24 clks AOUT7 AOUT1 AOUT3 AOUT5 AOUT2 AOUT4 AOUT6 24 clks AOUT8 DAC_SDIN4 AIN3 AIN5 AIN2 AIN4 AIN6 128 clks AOUT6 ADC/DAC_SCLK LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB DAC_SDIN1 AOUT1 AOUT4 AOUT2 AOUT5 AOUT3 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks AOUT8 LSB MSB LSB MSB AOUT7 32 clks 32 clks ADC/DAC_LRCK 256 clks MSB Bit or Word Wide LSB AIN6 LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB ADC_SDOUT1 AIN1 AIN4 AIN2 AIN5 AIN3 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks AUX2 LSB MSB LSB MSB AUX1 32 clks 32 clks MSB Figure 20. TDM Format |
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