CS42448 datasheet(38/70 Pages) CIRRUS

38 / 70 page

DS648PP2

4.7

Control Port Description and Timing

The control port is used to access the registers allowing the CS42448 to be configured for the desired

operational modes and formats. The operation of the control port may be completely asynchronous with

respect to the audio sample rates. However, to avoid potential interference problems, the control port pins

should remain static if no operation is required.

The control port has 2 modes: SPI and I²C, with the CS42448 acting as a slave device. SPI mode is se-

lected if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I²C

mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently

selecting the desired AD0 bit address state.

4.7.1 SPI Mode

In SPI mode, CS is the CS42448 chip select signal, CCLK is the control port bit clock (input into

the CS42448 from the microcontroller), CDIN is the input data line from the microcontroller, CD-

OUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK

and out on the falling edge.

Figure 23 shows the operation of the control port in SPI mode. To write to a register, bring CS

low. The first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is

a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory

Address Pointer (MAP), which is set to the address of the register that is to be updated. The next

eight bits are the data which will be placed into the register designated by the MAP. During

writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a

47 k

Ω resistor, if desired.

There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR

is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP

will autoincrement after each byte is read or written, allowing block reads or writes of successive

registers.

To read a register, the MAP has to be set to the correct address by executing a partial write cycle

which finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR)

may be set or not, as desired. To begin a read, bring CS low, send out the chip address and set

the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the ad-

MA P

MSB

LSB

DATA

by te 1

by te n

R/W

AD D R ES S

CH IP

ADDRESS

CHIP

CD IN

CC L K

CD OU T

MSB

LSB MSB

LSB

1001111

MAP = Memory Address Pointer, 8 bits, MSB first

High Impedance

Figure 23. Control Port Timing in SPI Mode

CS42448 数据表(PDF) 38 Page - Cirrus Logic

CS42448 数据表(HTML) 38 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

数据表下载