CS42448 datasheet(39/70 Pages) CIRRUS

39 / 70 page

DS648PP2

dressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is

set to 1, the data for successive registers will appear consecutively.

4.7.2 I2C Mode

In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock,

SCL. There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip ad-

dress and should be connected through a resistor to VLC or DGND as desired. The state of the

pins is sensed while the CS42448 is being reset.

The signal timings for a read and write cycle are shown in Figure 24 and Figure 25. A Start con-

dition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising

transition while the clock is high. All other transitions of SDA occur while the clock is low. The

first byte sent to the CS42448 after a Start condition consists of a 7 bit chip address field and a

R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at

10010. To communicate with a CS42448, the chip address field, which is the first byte sent to

the CS42448, should match 10010 followed by the settings of the AD1 and AD0. The eighth bit

of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address

Pointer (MAP) which selects the register to be read or written. If the operation is a read, the con-

tents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP

allows successive reads or writes of consecutive registers. Each byte is separated by an ac-

knowledge bit. The ACK bit is output from the CS42448 after each input byte is read, and is input

to the CS42448 from the microcontroller after each transmitted byte.

Since the read operation can not set the MAP, an aborted write operation is used as a preamble.

As shown in Figure 25, the write operation is aborted after the acknowledge for the MAP byte

by sending a stop condition. The following pseudocode illustrates an aborted write operation fol-

lowed by a read operation.

Send start condition.

Send 10010xx0 (chip address & write operation).

Receive acknowledge bit.

24 25

SCL

CHIP ADDRESS (WRITE)

MAP BYTE

DATA

DATA +1

START

ACK

STOP

ACK

0 AD1 AD0 0

SDA

INCR

16 17 18

10 11

13 14 15

27 28

DATA +n

Figure 24. Control Port Timing, I²C Write

SCL

CHIP ADDRESS (WRITE)

MAP BYTE

DATA

DATA +1

START

ACK

STOP

ACK

0 AD1 AD0 0

SDA

0 AD1 AD0 1

CHIP ADDRESS (READ)

START

INCR

12 13 14 15

20 21 22 23 24

26 27 28

10 11

17 18

ACK

DATA + n

STOP

Figure 25. Control Port Timing, I²C Read

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