Am29BDS643D

31

PRELI M INARY

AC CHARACTERISTICS

Notes:

1. Figure shows total number of wait states set to five cycles. The total number of wait states can be programmed from four

cycles to seven cycles (non-handshaking devices only).

2. Figure shows that PS (power saving mode) has been enabled; one additional wait state occurs during initial data Da. Latency

is not present if PS is not enabled.

3. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.

Figure 10.

Burst Mode Read (40 MHz)

Da

Da + 1

Da + 2

Da + n

OE#

A/DQ0:

A/DQ15

A16:

A20

Aa

AVD#

RDY

CLK

CE#

Aa

5 cycles for initial access shown.

Programmable wait state function is set to 01h.

1 cycle

wait state

when PS

enabled

25 ns typ.

Hi-Z

Hi-Z

Hi-Z