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AM29BDS643D 数据表(PDF) 39 Page - Advanced Micro Devices |
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AM29BDS643D 数据表(HTML) 39 Page - Advanced Micro Devices |
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39 / 46 page ![]() Am29BDS643D 39 PRELI M INARY AC CHARACTERISTICS Notes: 1. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. 2. If PS is enabled, RDY will be low for an additional cycle prior to the boundary crossing latency. Figure 18. Latency with Boundary Crossing CLK Address (hex) C60 C61 C62 C63 C63 C63 C64 C65 C66 C67 D60 D61 D62 D63 D64 D65 D66 D67 (stays high) AVD# RDY A/DQ0: A/DQ15 OE#, CE# (stays low) Address boundary occurs every 64 words, beginning at address 00003Eh: 00007Eh, 0000BEh, etc.) Address 000000h is also a boundary crossing. 3B 3C 3D 3E 3E 3E 3F 40 41 42 latency tRACC |
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