46

Am29BDS643D

PRELI M INARY

REVISION SUMMARY

Revision A (June 20, 2000)

initial release.

Revision A+1 (November 27, 2000)

Global

Deleted all references to non-handshaking option.

Ordering Information

Added “H’ designator to device package marking.

Requirements for Synchronous (Burst)

Read Operation

Changed the latency for address boundary crossing to

two cycles for all speeds of operation.

Autoselect Command Sequence

Corrected autoselect data for handshaking to 0041h.

Added table to section for feature clarification.

Chip Erase Command Sequence

Corrected the command sequence length during

unlock bypass mode from four cycles to two.

DC Characteristics table

Added specification for active burst mode current with

Program Command Sequence, Accelerated

Program Operation

Added text indicating that sectors must be unlocked

Table 4, Command Definitions

Corrected autoselect data for handshaking to 0041h.

AC Characteristics

rected RDY waveform to indicate behavior when PS

is enabled and when RDY is in the high-impedence

stage

.

Accelerated Unlock Bypass Programming Timing

Latency with Boundary Crossing (40 MHz) figure:

Deleted figure; all speed options have a two-cycle

latency.

Initial Access with Power Saving (PS) and Address

two-cycle latency is present, and that RDY is high for a

portion of the boundary latency.

Revision A+2 (November 30, 2000)

Figure 11, Asynchronous Mode Read

Figure 17, Toggle Bit Timings

(During Embedded Algorithm)

Corrected OE# waveform during second VA (valid

address) period.

Revision A+3 (December 21, 2000)

Figure 9, Burst Mode Read (54 MHz) and Figure 10,

Burst Mode Read (40 MHz)

Corrected RDY waveform.

Trademarks

Copyright © 2000 Advanced Micro Devices, Inc. All rights reserved.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.