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845GL 数据表(PDF) 39 Page - Intel Corporation |
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845GL 数据表(HTML) 39 Page - Intel Corporation |
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39 / 193 page  Intel® 82845G/82845GL/82845GV GMCH Datasheet 39 Signal Description 2.12 Reset States 2.12.1 Full and Warm Reset States All register bits assume their default values during full reset. A full reset occurs when PCIRST# (GMCH RSTIN#) is asserted and PWROK is deasserted. A warm reset occurs when PCIRST# (GMCH RSTIN#) is asserted and PWROK is also asserted. The following table describes the reset states. Figure 2-3. Full and Warm Reset Waveforms 1 ms min 1 ms min 1 ms min 1 ms min Write on CF9h ICH4 Power ICH4 PWROK In ICH4 PCIRST# Out GMCH RSTIN# In GMCH CPURST# Out GMCH Power GMCH PWROK In GMCH Reset State Unknown Full Reset Warm Reset Running Warm Reset Running Reset State RSTIN# PWROK Full Reset L L Warm Reset L H Does Not Occur H L Normal Operation H H |
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