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Intel® 82845G/82845GL/82845GV GMCH Datasheet

This chapter describes the platform device PCI configuration structure and register accesses

mechanisms. The chapter also provides a detailed description of the GMCH PCI configuration

registers including bit/field descriptions. The GMCH contains two sets of software accessible

registers, accessed via the host processor I/O address space:

• Control registers I/O mapped into the processor I/O space, which control access to PCI and

AGP configuration space (see section entitled I/O Mapped Registers)

• Internal configuration registers residing within the GMCH are partitioned into three logical

device register sets (“logical” since they reside within a single physical device). The first

device register set is dedicated to Host-Hub Interface Bridge functionality (controls PCI Bus 0

including DRAM configuration, other chipset operating parameters, and optional features).

The second device register set is dedicated to Host-AGP/PCI_B Bridge functions (controls

AGP/PCI_B interface configurations and operating parameters). The third device register set

is dedicated to the Integrated Graphics Device (IGD).

Note: This configuration scheme is necessary to accommodate the existing and future software

configuration model supported by Microsoft where the Host Bridge functionality will be supported

and controlled via dedicated and specific driver and “virtual” PCI-to-PCI bridge functionality will

be supported via standard PCI bus enumeration configuration software. The term “virtual” is used

to designate that no real physical embodiment of the PCI-to-PCI bridge functionality exists within

the GMCH, but that GMCH’s internal configuration register sets are organized in this particular

manner to create that impression to the standard configuration software.

The GMCH supports PCI configuration space accesses using the mechanism denoted as

Configuration Mechanism #1 in the PCI Local Bus Specification, Revision 2.1. The GMCH

internal registers (both I/O Mapped and Configuration registers) are accessible by the Host

processor. The registers can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities, with

the exception of CONFIG_ADDRESS which can only be accessed as a DWord. All multi-byte

numeric fields use “little-endian” ordering (i.e., lower addresses contain the least significant parts

of the field).

3.1

Term

Description

Read Only.

In some cases, If a register is read only, writes to this register location have no effect.

Write Only.

In some cases, If a register is write only, reads to this register location have no

effect.

R/W

Read/Write.

A register with this attribute can be read and written.

R/WC

Read/Write Clear.

A register bit with this attribute can be read and written. However, a write of 1

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