845GL datasheet(63/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.5.1.19

DRC—DRAM Controller Mode Register (Device 0)

Address Offset:

7C–7Fh

Default Value:

00000000h

Access:

R/W, RO

Size:

32 bits

Bit

Description

31:30

Revision Number (REV)—RO.

This field reflects the revision number of the format used for SDR/

DDR register definition. Currently, this field must be 00, since this (rev “00”) is the only existing

version of the specification.

Initialization Complete (IC)—R/W.

This bit is used for communication of software state between the

memory controller and the BIOS. BIOS sets this bit to 1 after initialization of the DRAM memory array

is complete.

Dynamic Power-Down Mode Enable—R/W.

When set, the DRAM controller will put pair of rows

into power down mode when all banks are pre-charged (closed). Once a bank is accessed, the

relevant pair of rows is taken out of Power Down mode.

The entry into power-down mode is performed by de-activation of CKE. The exit is performed by

activation of CKE.

0 = Disable.

1 = Enable.

27:10

Intel Reserved.

9:7

Refresh Mode Select (RMS)—R/W.

This field determines at what rate refreshes will be executed.

000 = Reserved

001 = Refresh enabled. Refresh interval 15.6 µs

010 = Refresh enabled. Refresh interval 7.8 µs

011 = Refresh enabled. Refresh interval 64 µs

111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode)

Other = Reserved

6:4

Mode Select (SMS)—R/W.

These bits select the special operational mode of the DRAM interface.

The special modes are intended for initialization at power-up.

000 =Post Reset state: When the GMCH exits reset (power-up or otherwise), the mode select field is

cleared to 000.

During any reset sequence, while power is applied and reset is active, the GMCH deasserts all

CKE signals. After internal reset is deasserted, CKE signals remain deasserted until this field is

written to a value different than 000. On this event, all CKE signals are asserted.

During suspend (S3, S4), GMCH internal signal triggers SDRAM controller to flush pending

commands and enter all rows into Self-Refresh mode. As part of resume sequence, GMCH will

be reset – which will clear this bit field to 000 and maintain CKE signals deasserted. After

internal reset is deasserted, CKE signals remain de-asserted until this field is written to a value

different than 000. On this event, all CKE signals are asserted.

001 =NOP Command Enable: All processor cycles to DRAM result in a NOP command on the

DRAM interface.

010 =All Banks Pre-charge Enable: All processor cycles to DRAM result in an “all banks precharge”

command on the DRAM interface.

011 = Mode Register Set Enable: All processor cycles to DRAM result in a “mode register” set

command on the SDRAM interface. Host address lines are mapped to SDRAM address lines

in order to specify the command sent. Host address HA[13:3] are mapped to memory address

MA[11, 9:0].

100 =Extended Mode Register Set Enable: All processor cycles to SDRAM result in an “extended

mode register set” command on the SDRAM interface (DDR only). Host address lines are

mapped to SDRAM address lines in order to specify the command sent. Host address lines are

mapped to SDRAM address lines in order to specify the command sent. Host address

HA[13:3] are mapped to memory address MA[11, 9:0].

101 =Reserved

110 = CBR Refresh Enable: In this mode all processor cycles to SDRAM result in a CBR cycle on the

SDRAM interface

111 = Normal operation

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